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Full-Time

Tech Lead Firmware Engineer

DDR technologies

Confirmed live in the last 24 hours

Astera Labs

Astera Labs

201-500 employees

Semiconductor connectivity solutions for AI and cloud

Hardware

Compensation Overview

$140k - $200kAnnually

Senior, Expert

Santa Clara, CA, USA

Category
Embedded Engineering
Software Engineering
Requirements
  • Bachelor’s in Electrical engineering / Electronics / Computer Science or related fields.
  • 5+ years of experience in developing Firmware using C in Embedded environments.
  • Good knowledge in DDR Technology internals (DDR Training, DDR RAS, PMIC, RCD etc.)
  • Ability to debug DDR related issues.
Responsibilities
  • Designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.
  • Post-Silicon bring up and validation of DDR memory interfaces.
  • Working with cross-functional teams and partners.
  • Pre-Silicon DDR bring up experience is a plus.
  • Experience with RDIMMs, DDR controller/PHY tuning is a plus.
  • Knowledge of Server memory performance and stability tuning for latency and bandwidth is a plus.

Astera Labs specializes in semiconductor-based connectivity solutions, including PCIe, CXL, and Ethernet technologies, designed to optimize cloud and AI infrastructure by addressing performance bottlenecks in data-centric systems. Their purpose-built products enable high-bandwidth, low-latency interconnects for compute, storage, and accelerator resources, as well as robust CXL and PCIe connectivity for GPUs, AI accelerators, and networking applications.

Company Stage

IPO

Total Funding

$739.4M

Headquarters

Santa Clara, California

Founded

2017

Growth & Insights
Headcount

6 month growth

18%

1 year growth

42%

2 year growth

117%