Lab Overview:

The Samsung SOC Lab vision provides innovative SoC architecture, NoC, memory subsystem, multimedia IPs, CPU, GPU, NPU blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and re-invent technology that will positively impact millions of people around the world via the Galaxy flagship products.

Position Summary:

We are looking for a CPU Microarchitecture and modeling engineer for next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to CPU core microarchitecture, performance and power tradeoffs.

Position Responsibilities:

• Guide on development of innovative CPU core microarchitectural features to boost PPA (Performance, Power and Area) on various targeted workloads in next generation SOCs
• Identify and deliver workload analysis driven CPU core microarchitecture features
• Evaluate architecture proposal benefits in collaboration with SoC Architects and communicate the microarchitecture proposals to audiences (Software, Hardware, Silicon Vendor, Architecture, Leadership, Product managers)
• Direct, orchestrate performance modeling studies [applications, benchmarks, and complex uses cases] to support inclusion of features in the next generation CPU core microarchitecture based on performance, area or power improvement
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System

Required Skills:

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training and experience
• 5+ years of experience in CPU design and microarchitecture
• Must have 5+ years of experience in coding microarchitecture features in C, C++, SystemC, Verilog or System Verilog
• High proficiency in CPU core microarchitecture analysis and modeling, ranging from simple analytical to complex cycle accurate models and driving correlation
• Highly proficient in simulation capabilities [GEM5, FastSIM, Platform Architect] or create new simulation capabilities when necessary
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), CPU core microarchitecture
• Leadership across hardware, software, and platform groups and aligning to a common vision