Full-Time

IC Package Engineer

Confirmed live in the last 24 hours

Etched.ai

Etched.ai

11-50 employees

Develops servers for transformer inference

No salary listed

Senior

Cupertino, CA, USA

In Person

Relocation support for those moving to Cupertino; housing subsidy of $2,000/month for those living within walking distance of the office.

Category
Hardware Engineering
Electronic Hardware Engineering
Requirements
  • Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, or related discipline
  • 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies
  • Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W
  • Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes
  • Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar
  • Familiarity with mechanical stress analysis, simulation, and validation methodologies
  • Solid communication skills to work across multi-disciplinary teams and external partners
Responsibilities
  • Own the end-to-end package design process, including substrate layout and IC package design, while collaborating with internal teams and external vendors to deliver optimized, manufacturable solutions
  • Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating stiffeners as needed
  • Expertise in large-scale BGA design, including experience with packages exceeding 4000-ball arrays, ball pitch optimization, routing, and power/ground plane design
  • Conduct mechanical and warpage analysis to address package warpage and coplanarity requirements across varying package sizes, collaborating with mechanical teams for simulation and testing to minimize thermal and mechanical stress
  • Perform design validation by assessing package layouts against electrical and mechanical constraints, providing design reviews and guidance on substrate and interconnect solutions, while archiving DFM-related learning for continuous improvement opportunities
  • Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams to ensure holistic package solutions, while interfacing with vendors to align design requirements and production feasibility
  • Oversee package reliability testing, including thermal, warpage, shock, shear, HTSL, HAST, ALT, JESD22, and electrical tests, while interfacing with various vendors to ensure compliance and quality
Desired Qualifications
  • Experience with advanced packaging nodes (e.g., 2.5D/3D stacking)
  • Knowledge of thermal management techniques in package design
  • Previous experience working in AI, HPC, or semiconductor design companies

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Company Size

11-50

Company Stage

Seed

Total Funding

$5.4M

Headquarters

Cupertino, California

Founded

2022

Growth & Insights

Headcount

6 month growth

800%

1 year growth

800%

2 year growth

800%