Principal Dft Design Engineer (Silicon Engineering)
Posted on 5/27/2022
Irvine, CA, USA
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 10+ years of experience working as block and full chip design for test (DFT) engineer
- Experience in DFT specifications, architecture, integration, methods and validation
- Knowledge about industrial standards, tools, and practices in DFT; including ATPG, JTAG, MBIST, LBIST and trade-offs between test quality and test time
- Verilog/SystemVerilog and DFT design verification methods, simulators and waveform debugging tools
- Experience in debugging compressed ATPG, MBIST and JTAG related issues
- Experience in STA constraints development and analysis for DFT modes and SDF simulations
- Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data
- Knowledge of ASIC synthesis, physical design flows, methodologies, clock domain crossing challenges and understanding DFT impact on those flows and tapeout signoff
- Experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT
- Experience with unified power format, formal verification and DRC rule checking experience
- Knowledge of deep sub-micron FinFET technology nodes (7nm and below) and DFT challenges associated with them
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
- Must be willing to travel when needed (typically <10%)
- Willing to work extended hours and weekends to meet critical deadlines, as needed
- This position can be based in either Redmond, WA, Irvine, CA, or Mountain View, CA
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here
- Develop/support automated block and full chip level DFT insertion flows and incorporate those flows into Physical design infrastructure
- Evaluate design readiness for scan insertion through RTL and physical design
- Run and evaluate scan insertion through synthesis tools and refine scan insertion recipes for maximum coverage
- Responsible for full chip test insertion, IEEE 1500, JTAG, boundary scan, block level MBIST/on chip clock controller insertion
- Run ATPG (Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
- Drive Scan/ATPG low coverage debug
- Integrate and verifiy DFT fabrics and IP within subsystems
- Scan timing closure, scan shift/scan capture mode timing constraint development
- Create ATPG vectors for use in post-silicon testing and validation of that content through gate level simulations
- Collaborate with circuit physical design team, ATPG team, and manufacturing team to facilitate high quality scan and memory BIST coverage in silicon
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- Reusability - SpaceX believes a fully and rapidly reusable rocket is the pivotal breakthrough needed to substantially reduce the cost of space access. The majority of the launch cost comes from building the rocket, which historically has flown only once.
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