Principal Memory Interface Systems Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Central Hardware Systems Group resides in Global Manufacturing Technology and Operations unit of Qualcomm Technology Inc., a leader in wireless communication technology. Engineers in the Interface Systems group work on mixed signal IP system architecture, interface standards, system-technology co-optimization, power and signal integrity, hardware/software co-design and post-Silicon bring-up to help create leading edge mobile, compute, and datacenter products.

Group is looking for engineers at senior levels with knowledge and experience in Memory (DDR5, LPDDR5/6, HBM3/4) interface IP and systems design.A successful candidate will be involved in Memory interface roadmap and spec definition, package/foundry technology co-optimization, signal/power integrity analysis and system KPI evaluations. The person will also work very closely with the cross-functional platform architecture, process technology, package engineering, IP and SoC development teams to successfully develop, test and deploy the design to end-product. Working effectively across organizational boundaries is essential as is effective documentation and presentation of results.

Responsibilities:  

• Memory interface landscape and roadmap alignment by working with Internal and External IP providers.
• PHY/Component models for early system exploration and Signal/Power Integrity solution space definition
• Translate product requirements to Memory IP system design spec
• System-technology co-optimization - SIPI, PDN, floorplan, PKG/PCB/Foundry technology, and IP PPA trade-off analysis to optimize system metrics such as cost, power, performance, and quality.
• Interface with cross-functional teams through various phases of the project to successfully integrate and validate the design.
• Coordinate system analysis activities with internal and/or 3rd party IP teams.
• Support silicon bring up and debug effort for Memory interfaces.
• Support post-Si correlation efforts and feedback to early design/proto-typing flows.
• Develop best known methods and establish guidelines for design teams to follow.
• Create clear and complete documentation of guidelines and results.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications

• MS or PhD in Electrical Engineering, or related discipline

Work experience:

• Knowledge of Memory-DDR5, LPDDR5/6, HBM3/4 standards is preferred.
• Experience in high-speed Memory PHY or systems design is preferred.
• Familiarity with Memory-DDR5, LPDDR5/6, HBM3/4 protocol, link training sequences and post-Si debug is a plus.

Skills:

• Ansys, Cadence, Keysight and MATLAB Tools, Hspice, Verilog

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Pay range and Other Compensation & Benefits:

$192,000.00 - $288,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.