Digital Design Engineer

Your Role in Our Mission

At Normal Computing, we’re developing a new thermodynamic computing paradigm to accelerate probabilistic AI workloads by embracing noise, rather than fighting it. Our work combines foundational research on the physics of computing with a mission to ship scalable, reliable silicon and systems to revolutionize AI.

As a digital design engineer at Normal, you will work closely with the silicon and hardware R&D team to develop and implement novel thermodynamic computing architectures. You will have significant ownership of the implementation of the digital interfaces, control logic, and error mitigation algorithms we need to implement our thermodynamic architectures. 

Responsibilities:

• You will play a key role in the entire development process of our silicon, from idea to architecture to implementation to tape-out.

• Contribute new ideas for potential thermodynamic computing technologies and architectures.

• Implement digital components on our ASICs and in our FPGA test harness, potentially including serial and parallel interface controllers, signal processing algorithms, and calibration algorithms.

• Support physical implementation of digital logic on ASICs and FPGAs using Cadence and Xilinx tools, respectively.

• Develop FPGA-based harnesses and systems.

• Participate in the tape-out, bring-up, and testing of Normal’s silicon.

What Makes You A Great Fit:

• Strong experience in Verilog and/or SystemVerilog.

• Fluent in C and/or C++.

• Understanding of best practices of testbench design.

• Experience in scripting languages, including Python, Perl, and/or TCL.

• Experience achieving timing closure on a complex design.

• Proficiency with FPGA tools and flows, especially Xilinx Vivado.

• Excellent communication skills and the ability to work well on a small, interdisciplinary team.

What Elevates Your Application:

• Experience working with VerilogA blocks or on complex mixed-signal systems.

• Experience with all-digital or mixed-signal PLL design.

• Experience with asynchronous logic.

• Proficiency with Cadence RTL-to-GDSII flows, including Genus, Innovus, Tempus, or Voltus.

• Experience selecting, sourcing, and integrating third-party IP from multiple different vendors into a silicon product.

• Familiarity with the wafer test, packaging, and chip testing process, including creating package drawings, writing test plans, and working with an external testing provider to implement testing at scale.

• Experience working at a startup.

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.