Full-Time

Principal Verification Engineer I

Confirmed live in the last 24 hours

CesiumAstro

CesiumAstro

51-200 employees

Develops communication payloads for air and space

Hardware
Aerospace

Senior

El Segundo, CA, USA

Required Skills
Verilog
Python
MATLAB
VHDL
FPGA
Linux/Unix
Requirements
  • A Bachelor of Science (BS) or Master of Science (MS) degree in Computer Science, Electrical Engineering, or Computer Engineering.
  • Minimum of 9 years of industry experience in verification and automation.
  • Expert-level knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.
  • Expert-level knowledge of digital design automation infrastructure, including CI, regression testing and HIL testing.
  • Advanced-level knowledge of Linux.
  • Advanced-level knowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.
  • Desire and ability to train and mentor while maintaining a positive and productive attitude.
  • A deep sense of ownership of your work, and for the success of the company.
Responsibilities
  • Lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure.
  • Lead the development, maintenance and phased deployment of continuous integration and regression testing infrastructure.
  • Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models.
  • Lead the development of reusable custom VIP modules.
  • Work closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design.
  • Work with the modeling and scientific staff to implement DPI-C dataplane verification interfaces into existing MATLAB and Python models.
  • Regularly communicate and present on the current state of verification in the industry, and at the company.
  • Continually evaluate current processes regarding FPGA and digital design with a focus on Xilinx TLM models and QEMU-RP integration.
  • Work closely with vendors to define requirements of future simulation model deliverables.
  • Maintain up-to-date knowledge of industry best-practices regarding FPGA and digital design methodologies.
  • Work closely with the engineering leadership team to evaluate and non-disruptively implement process improvements.

CesiumAstro specializes in developing software-defined phased array communication payloads for both airborne and in-orbit platforms, offering full-stack mission-ready communications for the Autonomous Era™. Their products include the VIREO multi-beam APA system, NIGHTINGALE I Ka-Band high-speed downlink payload, and the COMMPACK cross-link communications payload, all featuring modular hardware and software building blocks seamlessly integrated to provide complete mission-specific payload configurations. These products utilize active phased array systems and digital backend modules to support high-throughput communication needs.

Company Stage

N/A

Total Funding

$120.2M

Headquarters

Austin, Texas

Founded

2017

Growth & Insights
Headcount

6 month growth

16%

1 year growth

44%

2 year growth

95%