New Grad CPU Verification Engineer
AI Silicon
Confirmed live in the last 24 hours
Locations
Santa Clara, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
C/C++/C#
Verilog
VHDL
Requirements
- BS/MS/PhD in EE/ECE/CE/CS with a strong GPA
- Knowledge of computer architecture/system components/network/fabric, prior internship working in these domains preferred
- Strong academic skills or internship experience in verification methodologies and techniques - Simulation/debug, TB development, stimulus, checking, coverage
- Academic projects in C++ / SV / UVM as well knowledge of scripting languages
- Understanding of assembly level programming
- Knowledge of hardware description languages (Verilog, VHDL)
- Strong problem solving and debug skills across various levels of design hierarchies
Responsibilities
- Develop DV testplans for ISA and microarchitecture and execute on them
- Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers and coverage models
- Build architectural tools for ISA level verification
- Develop stimulus generators that scale from pre-silicon to emulation and post-silicon domain
- Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
Desired Qualifications
- Understanding of deep learning concepts and familiarity with popular machine learning frameworks and models is a plus