Digital Design Engineer – Principal
Micro-Architect
Posted on 3/23/2024
d-Matrix

51-200 employees

AI inference platform with IMC technology
Company Overview
d-Matrix stands out in the AI compute platform sector by specifically targeting the energy and cost challenges of large-scale AI inference with their in-memory computing (IMC) techniques and chiplet level interconnects. Their approach has led to a more efficient integration of memory and compute resources, which is critical for the demanding workloads of generative AI and large language models. By offering a scalable solution that adapts to various model sizes, d-Matrix provides a sustainable and economically viable platform for companies facing the growing energy demands of AI technologies.
Data & Analytics
Hardware
AI & Machine Learning
B2B

Company Stage

Series B

Total Funding

$161.5M

Founded

2019

Headquarters

Santa Clara, California

Growth & Insights
Headcount

6 month growth

2%

1 year growth

50%

2 year growth

343%
Locations
Santa Clara, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
CategoriesNew
AI & Machine Learning
Applied Machine Learning
Robotics & Autonomous Systems
Deep Learning
Requirements
  • BSEE + Master’s degree in electrical engineering, Computer Engineering or Computer Science with 5 years of meaningful work experience.
  • Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on high-speed Processor and sub-system design, Digital Signal Processing blocks.
  • Exposure to Mixed-signal designs, Computer Architecture & Arithmetic is required.
  • Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
  • Strong interpersonal skills and an excellent teammate.
  • Experience with RISC V/Tensilica/ARM/Mips processors.
Responsibilities
  • Responsible for the micro-architecture and design of the AI sub-system modules including SIMD, Hardware Execution Engines.
  • Definition and implementation of Custom ISA.
  • Work with System Architects to develop efficient C-Kernel utilizing the Custom ISA.
  • Design, document, execute and deliver fully verified, high performance, area, and power efficient RTL to achieve the design targets and specifications.
  • Design and implement logic functions that enable efficient test and debug and participate in silicon bring-up and validation for blocks owned.