What You’ll Do

The Technology Enabling and Development (TED) Lab is part of Samsung’s Memory Business Unit, the industry’s technology and volume leader in DRAM, NAND Flash, and SRAM memory.  TED has the charter to develop SSD for enterprise customers. More recently, TED has also been tasked to develop SSD controller architecture to support future enterprise SSD designs. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams across geographically distributed sites to bring innovation to enterprise SSD product road maps.

You will be a key technical member of TED Controller Architecture Team and will be responsible for designing and developing high level architecture for SSD controllers. You will join a team of experts in researching and developing innovative high level controller chip architecture for data center/cloud and enterprise SSD. The ideal candidate must have prior experience developing high level chip and system architecture of leading-edge high performance SSD devices.

The SOC Architect will be responsible for developing, contributing, and leading ASIC high level-architecture activities in SSI storage-based controllers. The successful hire will have strong knowledge of latest trends in NVMe standards, data center/enterprise customer technical requirements, and knowledge/experience of end to end SSD controller chip architecture. The job scope will cover technical requirement analysis, architecture specifications, high level design/flows, and architecture modeling for architecture level assessment of high level building blocks and flows using state of the art advance development tools and methods before microarchitecture and RTL development.

Location: Hybrid, working onsite at our San Jose, CA headquarters 3 days a week, with the flexibility to work remotely the remainder of your time the remainder of your time with an average of 25% travel per year.

Job ID: 41246

• Engage and Review standards and technical customer requirements at product, system, and firmware level.
• Analyze requirements for chip design, prepare architecture specifications, high level design/flows, and work closely with model development and microarchitecture team for architecture assessment and chip development.
• Evaluate and Assess tradeoffs using architecture level transactional and LT models for ease of implementation, leverage, scalability, and PPA.  
• Research architectural trade-offs of enterprise/data-center storage controller ASIC.
• Write and maintain High Level Architecture Specification.
• Research emerging technology NVMe/Multi-tenancy standards, interconnects and map to optimal implementation in SOC and help develop new IP for high performance and mainstream enterprise/data-center SSDs.
• Analyze storage workloads to identify performance bottlenecks and opportunities.
• Collaborate with Microarchitecture/RTL team to ensure high level architecture intent is preserved during SOC and product development.
• Perform self-guided performance simulation studies of design alternatives.
• Work with other hardware/software architects developing one of a kind innovative Enterprise Storage models, MPW, and Controllers to ensure critical chip architecture assessment and decisions are made early enough in the design cycle.
• Propose and execute on innovations in software and hardware storage controller architecture based on their benefits to large-scale enterprise applications.

What You Bring

• BS with 15 years, MS with 13 years or PhD with 10 years in Computer Engineering or Electrical Engineering with SoC design and architecture experience.
• Extensive experience with ARM microprocessor, interconnect, memory, storage SoC systems architecture.
• Demonstrated record of architecting, designing and delivering complex and high-performance hardware SoC systems and high density storage using flash.
• Exposure and understanding of storage workloads and benchmark performance.
• Experience in NVMe and multitenancy controller architecture. Solid experience in PCIe and NVMe interfacing and understanding of I/O protocols
• Experience analyzing storage workloads.
• Storage interfaces and protocols: PCIe, NVMe, and Evolving standards like ZNS, ZRWA, Open Channel, and other similar protocols.
• Network interfaces and protocols: Ethernet, RoCE v1/v2, and Infiniband.
• Flash technology: Toggle, ONFI, FTL,
• Familiarity with all aspects of chip architecture and development: requirements, architecture specifications, high level design/model, microarchitecture design, firmware, and System.
• Demonstrated hands-on experience writing detailed chip architecture specifications and implementation details.
• Provide architectural guidance throughout the design process beyond architecture model to microarchitecture and implementation.
• A strong knowledge through academic coursework or experience in NAND memory systems, as well as other memory types.
• Platform level architectures and performance. Strong exposure to performance analysis and design tradeoffs. Strong working knowledge of architecture tradeoff analysis and modeling tools, commercial and in-house.  Exposure to SW development practices.
• Demonstrated problem solving and troubleshooting skills.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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