Senior Physical Design Engineer
Posted on 3/22/2024
Groq

201-500 employees

Delivers ultra-low latency AI inference solutions
Company Overview
Groq is a leading AI solutions company that stands out for its ultra-low latency AI inference and unique Language Processing Unit™, offering a synchronous ecosystem for rapid inference at scale. The company's solutions, entirely designed, engineered, and manufactured in North America, are readily available despite industry challenges, showcasing their competitive advantage in supply chain management. With a proven track record of reducing developer complexity and accelerating time-to-production, Groq fosters a culture that values human capital and technological performance, making it an attractive workplace for those seeking to contribute to cutting-edge AI technology.
Hardware

Company Stage

Series C

Total Funding

$408.6M

Founded

2016

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

17%

1 year growth

13%

2 year growth

2%
Locations
Remote in USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Python
Perl
CategoriesNew
Hardware Engineering
Electronic Hardware Engineering
System Hardware Engineering
Requirements
  • BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.
  • 8+ years of meaningful industry experience and a background in block/top level physical design of high-speed processors (i.e. Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs)
  • Strong hands on experience in implementing multi-voltage, multi-clock domain designs
  • Expert in different CTS methodologies, global and block level clock distribution
  • Strong experience with Static Timing Analysis from defining methodologies to running STA at block and top level.
  • Expert in implementing PD power optimization techniques and have a keen eye to look for power reduction options throughout the PD cycle.
  • Strong understanding of timing constraints, timing analysis, power grid design, power analysis (EMIR/di/dt), ECO generation and MCMM STA signoff
  • Deep understanding of low power format like UPF/CPF
  • Experience in formal equivalency checks, Low Power Rule check and verification.
  • Expert in industry standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX
  • Strong Automation skills using scripting languages like TCL, Python, Perl etc.
Responsibilities
  • Technical Lead for full chip integration activities; drive development and deployment of methodologies for these tasks both internally and with ASIC design partner in leading technology nodes.
  • Own and drive the overall Global Clock design including simulations and work closely with ASIC design partner in implementing the Global Clocks.
  • Lead and own Sign-off activities like STA, EMIR, Physical Verification from defining the methodology to running these at block and full chip level.
  • Own and drive execution of blocks from Synthesis, P&R to Timing Sign-off, Physical Sign-off and Electrical Sign-off.
  • Collaborate closely with the Microarchitecture/RTL team to help drive PPA improvements and resolve design issues.
  • Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach.