Full-Time

FPGA Engineering Lead

Posted on 4/18/2024

Ouster

Ouster


Senior

San Francisco, CA, USA

Required Skills
Bash
Verilog
Python
Communications
Perl
VHDL
FPGA
Requirements
  • Bachelors in Computer Engineering, Electrical Engineering, or related field
  • At least 5 years FPGA development experience including HDL code development, simulation, test bench development, synthesis, and timing closure
  • Experience and understanding of safety concepts and ISO 26262, ASIL-B, or similar standards
  • Highly proficient with RTL development using Verilog and SystemVerilog
  • Proficient in some scripting languages such as Python, TCL, Perl, bash
  • Embedded system development experience in CPU and FPGA based devices such as Xilinx Zynq or Intel Arria devices
  • Experience with Xilinx and/or Intel FPGA toolchain
  • Experience with DSP algorithm implementations in FPGAs
  • Experience with processor architectures and various communications protocols such as DDR4, AXI, I2C, UART, SPI, ethernet, etc.
Responsibilities
  • Lead and perform safety analysis of FPGA subsystems
  • Drive and create functional safety documentation including V model requirements and FMEDA analysis
  • Define, develop, and integrate features across our FPGA stack with a focus on functional safety and reliability.
  • Enforce and refine FPGA development process to support functional safety needs.
  • FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis
  • Perform hands-on work using laboratory tools for board bring up and troubleshooting
  • Build automation scripts for repetitive tasks to facilitate efficiency and reliability

Company Stage

N/A

Total Funding

N/A

Headquarters

N/A

Founded

N/A