FPGA Engineer

• Define and develop Field-Programmable Gate Array (FPGA) based hardware solutions, creating detailed micro-architecture specifications for custom accelerator, storage, and networking systems. Drive the entire FPGA development lifecycle, including IP integration, synthesis, floor planning, timing closure, and hardware bring-up and debug.
• Implement, optimize, and verify high-quality Register-Transfer Level (RTL) code using SystemVerilog, ensuring designs meet critical performance, power, and area goals.
• Collaborate closely with Software, Systems, and Silicon Engineering teams to ensure seamless hardware/software integration and contribute to the development of end-to-end solutions.
• Develop and maintain verification test benches and automated build flows to ensure design quality, and troubleshoot complex issues in deployed systems at data center scale.
• Lead the bring up, validation, New Product Introduction (NPI), deployment, and sustaining of hardware solutions. Drive system development from concept through production.

Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• 4 years of experience working in an ASIC or FPGA design technical environment, or 3 years of experience with an advanced degree.
• Experience with Register-Transfer Level design using Verilog or SystemVerilog.
• Experience in the FPGA/ASIC development lifecycle, including synthesis, timing closure, and logic simulation.
• Experience with common hardware communication protocols such as Ethernet, PCIe, I2C, and SPI and common on chip system bus protocols such as AXI4, Avalon etc.
• Experience with FPGA design and verification tools (Vivado, Quartus) and industry-standard simulation software.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership, leading FPGA projects or ASIC block development.
• Experience with version control systems such as Git or Perforce for collaborative code development.
• Experience with hardware and system design, and deploying and debugging hardware products in a large-scale data center environment.
• Experience with server management technologies such as Data Center-Secure Control Module (DC-SCM), Low-voltage differential signaling Tunneling Protocol and Interface (LTPI), and system bootstrapping logic.
• Proficiency with scripting languages for automation, such as Python or Tcl.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex, enabled by custom hardware designed and made in-house.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

• PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• 4 years of experience working in an ASIC or FPGA design technical environment, or 3 years of experience with an advanced degree.
• Experience with Register-Transfer Level design using Verilog or SystemVerilog.
• Experience in the FPGA/ASIC development lifecycle, including synthesis, timing closure, and logic simulation.
• Experience with common hardware communication protocols such as Ethernet, PCIe, I2C, and SPI and common on chip system bus protocols such as AXI4, Avalon etc.
• Experience with FPGA design and verification tools (Vivado, Quartus) and industry-standard simulation software.