Responsibilities

• Collaborate with the software team and platform architecture team to understand fabric bandwidth and latency requirements and real-time constraints for AI accelerator, CPU, security, and networking traffic. Devise QoS and ordering rules among the CPU, accelerator, and IO coherent/non-coherent traffics.
• Identify representative traffic patterns for the software applications. Perform data-driven analysis to evaluate fabric topology, QoS, memory architecture , and u-architecture solutions to improve performance, power efficiency, or reduce hardware.
• Create directory-base cache coherency specification to satisfy performance requirements of coherent multiple-cluster CPU system and accelerator. Tradeoff protocol complexity and performance requirements.
• Design cache hierarchy to create best performance
• Set SoC architecture direction based on the data analysis and work with a cross-functional team to achieve the best hardware/software solutions to meet PPA goals.
• Develop a SoC cycle-accurate performance model includes memory sub-systems, directory-base coherent cache controllers, fabric interconnects, and fabric switches that describes the microarchitecture, use it for evaluation of new features.
• Collaborate with RTL and Physical design engineers to make power, performance, and area trade-offs.
• Drive analysis and correlation of performance feature both pre and post-silicon.

Experience and qualifications:

• BS/MS/PhD in EE/ECE/CE/CS
• Strong grasp of NoC topologies, routing algorithms, queuing, traffic scheduling, and QoS requirements.
• Expertise in cache coherency protocols (AMBA CHI/AXI protocol), DDR/LPDDR/GDDR memory technology, and IO technology (PCIe/CCIX/CXL).
• Prior experience or strong understanding of traffic patterns for ML/AI algorithms in a heterogeneous computation system is a plus.
• Prior experience on formal verification of cache coherency protocol is a plus.
• Proficient in C/C++ programming. Experience in the development of highly efficient C/C++ CPU models.