Semiconductor Packaging Engineer
Updated on 1/31/2024
Astera Labs

201-500 employees

Semiconductor-based connectivity solutions for cloud-scale data
Company Overview
Astera Labs stands at the forefront of semiconductor-based connectivity solutions, specializing in the optimization of accelerated computing platforms for AI applications. Their pioneering products, based on PCIe, CXL, and Ethernet technologies, address the growing demand for efficient data processing, transfer, and storage in today's data centers. With a focus on enabling intelligent data infrastructure at cloud-scale, Astera Labs is a key player in supporting the vast majority of organizations investing in big data and AI initiatives.
Hardware

Company Stage

Series D

Total Funding

$232.4M

Founded

2017

Headquarters

Santa Clara, California

Growth & Insights
Headcount

6 month growth

14%

1 year growth

42%

2 year growth

181%
Locations
Santa Clara, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Printed Circuit Board (PCB) Design
Cadence Allegro
CategoriesNew
Hardware Engineering
Requirements
  • MS/PhD in Electrical Engineering
  • Minimum of 5 years of experience in packaging SI/PI analysis and optimization
  • Hands-on experience in using package and PCB extraction tools such as ANSYS 3DLayout, HFSS or SIwave
  • Experience of independently driving package development from concept to production in the NPI cycle
  • Deep knowledge of industry best known design method and commonly used SI/PI optimization techniques
  • Working knowledge of typical high-speed industry protocols such as PCIe, SERDES, Ethernet, DDR, CXL, etc.
Responsibilities
  • Utilizing expertise in signal and power integrity to optimize package and system-level performance
  • Managing package engineering tasks throughout the product lifecycle
  • Collaborating with chip and package design, manufacturing, and hardware engineering to meet program goals
  • Emphasizing the critical aspect of system-level SI/PI
Desired Qualifications
  • Allegro Package Designer (APD) experience to view, edit or verify designs for optimization iterations and package sign-off
  • Experience of DDR channel simulation analysis
  • Experience with electrical measurement equipment such as VNA, oscilloscope, and TDR