Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
As an Astera Labs Senior Semiconductor Packaging Engineer, you’ll be developing connectivity products for leading cloud service providers and server/networking OEMs. Your primary focus will be utilizing your expertise in signal and power integrity to optimize package and system-level performance. Your role involves managing package engineering tasks throughout the product lifecycle, collaborating with chip and package design, manufacturing, and hardware engineering to meet program goals, including schedule, cost, and manufacturing requirements, all while emphasizing the critical aspect of system-level SI/PI.
Basic qualifications:
- MS/PhD in Electrical Engineering
- A minimum of 5 years of experience in packaging SI/PI analysis and optimization, encompassing interconnections at various levels (chip, package, and PCB).
- Hands-on experience in using package and PCB extraction tools such as ANSYS 3DLayout, HFSS or SIwave and developing complete SI/PI models and performing system-level analysis for package optimization and tape-out.
- Experience of independently driving package development from concept to production in the NPI cycle by working cross-functionally with both internal teams and external suppliers.
- Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks. Working with minimal guidance and supervision to deliver solutions.
Required experience:
- Experience of extracting FCBGA package SI models such as s-parameter and SPICE.
- Experience of performing complete PDN analysis such as DCIR, power tree, loop inductance, target impedance and AC time domain analysis.
- Experience of using circuit and system level analysis tools (such as Keysight ADS) to drive chip + package + PCB simulation, optimization and sign-off (ERL, eye-diagram, transient response, etc.).
- Deep knowledge of industry best known design method and commonly used SI/PI optimization techniques.
- Working knowledge of typical high-speed industry protocols such as PCIe, SERDES, Ethernet, DDR, CXL, etc.
- Able to perform simulation-to-measurement correlation analysis, and refine modeling methodology and flow, to ensure real-world performance match design expectations.
- Understanding of FCCSP and FCBGA packages from perspectives of electrical performance, material characteristics, manufacturing, BOM, supply chain, reliability, risk management and failure analysis.
- Experience of working directly with substrate suppliers and OSAT vendors in package development cycle.
Preferred experience:
- Allegro Package Designer (APD) experience to view, edit or verify designs for optimization iterations and package sign-off.
- Experience of DDR channel simulation analysis is a plus.
- Experience with electrical measurement equipment such as VNA, oscilloscope, and TDR is a plus.
The base salary range is $120,000.00 USD – $170,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
