Job Description:

In this role you will drive the innovative System Architecture for high-speed analog Serdes (low-power, high-performance AMS solutions customized for AI application).

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Understanding digital signal processing and digital communications for optical interfaces
• Modelling/simulation/analysis of systems including high speed analog components (ADC, DAC, drivers, TIA), opto-electronic components (optical modulators, optical mixers, photodiodes, lasers, optical mux/demux, optical amplifiers), fiber impairments (CD, PMD, non-linearities) and DSP algorithms (calibration of analog and optical nonidealities, equalizers, carrier frequency/phase recovery, timing recovery)
• Analysis and modelling of systems to drive definition of standards in OIF/IEEE/ITU-T
• Work with lab equipment (spectrum analyzers, scopes, VOA, lasers, ASE generators etc.)
• Design experiments to collect/analyze data to enable definition of next generation DSP
• Debug complex optical, analog and signal processing problems
• Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers
• Create DSP and FEC hardware block specifications appropriate for RTL implementation
• Perform research activities in digital signal processing for SerDes and optical channels
• Work with designers to ensure circuit architecture can be efficiently implemented
• Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers
• Provide guidance on test plans for lab characterization once design comes back from fab
• Participate in chip lab bring up
• Should be comfortable working with lab equipment

QUALIFICATIONS:

• Requires master’s degree with 6+ years of experience in related areas of expertise or PhD with 3+ years of experience
• Knowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standards
• Strong experience in communication system modeling in Matlab, C and/or Python
• Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR)
• Experience with FEC (RS, soft decoding, Viterbi algorithm)
• Experience with high-speed Analog Serdes and the associated calibration algorithms
• Experience with debugging complex analog issues to improve system performance is required
• Knowledge of digital design of DSP blocks will be a huge plus

Location:  This role can be based out of Santa Clara, CA, Orange County, CA or Toronto, Ontario, Canada

For California location:

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity.  The target base salary for this role is approximately $175,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.