Principal Digital Design Engineer

Confirmed live in the last 24 hours

201-500 employees

Semiconductor-based connectivity solutions for cloud-scale data

Company Overview

Astera Labs stands at the forefront of semiconductor-based connectivity solutions, specializing in the optimization of accelerated computing platforms for AI applications. Their pioneering products, based on PCIe, CXL, and Ethernet technologies, address the growing demand for efficient data processing, transfer, and storage in today's data centers. With a focus on enabling intelligent data infrastructure at cloud-scale, Astera Labs is a key player in supporting the vast majority of organizations investing in big data and AI initiatives.

Hardware

Company Stage

Series D

Total Funding

$382.4M

Founded

2017

Headquarters

Santa Clara, California

Growth & Insights

Headcount

6 month growth

↑ 11%

1 year growth

↑ 33%

2 year growth

↑ 167%

Locations

Toronto, ON, Canada

Experience Level

Entry

Junior

Mid

Senior

Expert

Desired Skills

Python

CategoriesNew

AI & Machine Learning

Software Engineering

Requirements

Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred
10+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in Canada and start immediately
Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc
Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Cadence and/or Synopsys digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design

Desired Qualifications

Firmware development with C-language, scripting with Python or other equivalent programming languages
Development/support for PCIe or Ethernet Switch products

Astera Labs is a global leader delivering semiconductor-based connectivity solutions purpose-built to unleash the full potential of intelligent data infrastructure at cloud-scale. Our class-defining first-to-market products based on PCIe, CXL, and Ethernet technologies deliver critical connectivity for high-value artificial intelligence and machine learning applications. Our focus on customer-driven product definition and commitment to design solutions in the cloud, for the cloud, results in breakthrough execution and scale for our customers. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.

Job Description

We are looking for a Principal Digital Design Engineer with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic qualifications:

Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in Canada and start immediately.

Required experience:

Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Cadence and/or Synopsys digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design

Preferred experience:

Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.