Full-Time

Power Integrity Engineer

Lumilens

Lumilens

51-200 employees

Photonic interconnects for AI data centers

No salary listed

India

In Person

Category
Electrical Engineering (1)
Required Skills
Printed Circuit Board (PCB) Design
Python
MATLAB
Oscilloscope
Requirements
  • Bachelor’s or Master’s in Electrical/Electronics Engineering, with focus on RF/mixed-signal design.
  • 5+ years in Power Integrity for high-speed transceivers (OSFP, QSFP-DD, or CDFP preferred); hands-on with 50G+ SerDes.
  • Proficiency in PI tools (Ansys, HyperLynx, Sigrity) and scripting (Python/MATLAB) for automation.
  • Strong understanding of power converter topologies (Buck/Buck-Boost), equivalent series inductance modeling, and electromagnetic interference/EMC mitigation.
  • Experience with OSFP mechanical constraints, flex-rigid printed circuit boards, and multi-die integration (e.g., co-packaged optics).
Responsibilities
  • Perform PI simulations using tools like Ansys SIwave, Keysight ADS, or Cadence Sigrity to model and optimize PDN for OSFP modules, targeting <1mΩ target impedance across 10kHz-100MHz bandwidth.
  • Analyze and mitigate power rail decoupling, voltage regulators modules, and bypass capacitor placement for multi-rail supplies (0.8V core, 1.8V I/O, 3.3V aux) in high-current OSFP designs up to 100W+.
  • Collaborate on PCB stackups, via optimization, and plane splitting to reduce simultaneous switching noise and ground bounce in 112G PAM4 SerDes environments.
  • Validate designs through lab measurements using VNA, oscilloscopes, and power analyzers; correlate simulations with hardware prototypes.
  • Support signal integrity co-optimization, thermal-PD synergy (e.g., integrating thermal interface materials with PDN), and compliance to IEEE 802.3ck/802.3df standards.
  • Document PI reports, contribute to design reviews, and mentor junior engineers on best practices for hyperscale OSFP deployments.
Desired Qualifications
  • Familiarity with thermal co-simulation (e.g., Ansys Icepak integration) for heat-affected PDN performance.
  • Knowledge of advanced materials like low-dielectric-constant dielectrics or embedded passives for PDN miniaturization.
  • Prior work on 1.6T OSFP or Co-Packaged Optics prototypes.

Lumilens develops high-speed photonic interconnects for AI data centers, providing optical transceivers and packaging that connect compute across scale-out clusters and scale-up GPU-to-GPU links. Its products include silicon-photonics-based 800GbE DR8 and 2x400GbE FR4 transceivers, using advanced packaging such as near-packaged and co-packaged optics. The company designs its own silicon and uses AI-optimized automated manufacturing to boost yield and ensure supply continuity across global facilities. Lumilens aims to enable massive AI compute growth by delivering scalable optical interconnects that outperform traditional electrical links and legacy optics, while addressing evolving geopolitical requirements.

Company Size

51-200

Company Stage

N/A

Total Funding

N/A

Headquarters

San Jose, California

Founded

2024

Simplify Jobs

Simplify's Take

What believers are saying

  • Raised $133M from Spark Capital and secured $106M Series B from Accton in April 2025.
  • Team scaled to 100-200 employees by late 2025 for production ramp-up.
  • Actively hiring 43 roles in San Jose signals design hub expansion.

What critics are saying

  • Broadcom's 1.6T optics in Nvidia Blackwell crushes Lumilens' 800G in 6-12 months.
  • Ayar Labs' 4Tbps chiplet in AMD MI400 obsoletes pluggable optics in 12-18 months.
  • Thailand floods drop yields 20%, delaying FR4 shipments in 3-6 months.

What makes Lumilens unique

  • Lumilens designs in-house silicon photonics for scale-out and scale-up AI interconnects.
  • Custom robotics and AI-optimized manufacturing ensure supply chain continuity.
  • Supports 800GbE DR8 and 2x400GbE FR4 transceivers for datacenter optics.

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