Full-Time

SOC Physical Design Verification Engineer

Full Time

Confirmed live in the last 24 hours

Rivos

Rivos

201-500 employees

High performance RISC-V computing solutions

Hardware

Mid

Austin, TX, USA + 3 more

Required Skills
Python
Requirements
  • Deep understanding of the challenges associated with in deep sub-micron process nodes
  • Hands-on experience in closure and tapeout of large hierarchical designs
  • Experience with industry standard physical verification tools (Siemens Calibre)
  • Strong scripting skills in tcl and python
  • Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
  • Self starter and highly motivated
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules
Responsibilities
  • Develop PDV methodology and infrastructure for verification flow of large SoCs
  • Perform full chip integration and run physical verification checks
  • Provide guidance to implementation teams for early convergence and final closure
  • Interface with internal and external design teams for quality deliverables
  • Work with package and floorplan teams for padring and bump map design
  • Collaborate with technology team to define flows and integrate foundry PDK data

Rivos provides a compelling work environment for those keen on contributing to leading-edge computing solutions in the enterprise sector. The company is a specialist in leveraging high-performance RISC-V systems, positioning it as a key player in the advanced computing niche. Working here exposes employees to cutting-edge technology and significant industry challenges, nurturing a culture of innovation and technical excellence.

Company Stage

Series A

Total Funding

$250M

Headquarters

Santa Clara, California

Founded

2021

Growth & Insights
Headcount

6 month growth

4%

1 year growth

0%

2 year growth

47%