Full-Time

CAD/EDA Engineer 1 – Senior CAD/EDA Engineer

CAD/EDA Engineer II, Texas Institute for Electronics

Posted on 2/21/2026

University of Texas at Austin

University of Texas at Austin

No salary listed

No H1B Sponsorship

Austin, TX, USA

In Person

On-site at Pickle Research Campus, Austin, TX; relocation assistance may be available.

Category
Electrical Engineering (1)
Requirements
  • CAD/EDA Engineer I: Bachelor’s degree in Electrical Engineering, Computer Science or closely related field.
  • CAD/EDA Engineer II: Bachelor’s degree in Electrical Engineering, Computer Science or closely related field, Minimum of three years industry experience.
  • Senior CAD/EDA Engineer: Bachelor’s degree in Electrical Engineering, Computer Science or closely related field, Minimum of ten years industry experience.
  • Experience in developing and customizing high performance semiconductor integrated circuit design, layout, and validation flows using industry-standard electronic design automation tools (Cadence, Synopsys, Ansys, Siemens…).
  • Excellent UNIX and scripting programming skills (Perl, Python, TCL or similar languages).
  • Experience with software build automation and version control software.
  • Proficiency in both Linux and Windows environments.
  • Prior CAD support experience in semiconductor integrated circuit design, including oversight of product tapeouts.
  • Strong teamwork, collaboration, and communication abilities, with the ability to contribute to company-wide consensus on design flows, tools, and methodologies.
  • Ability to thrive in a fast-paced environment and manage multiple projects simultaneously.
  • Relevant education and/or industry experience may be substituted as appropriate.
Responsibilities
  • Create and maintain scripts/automation to assure compatibility and integration with wide range of EDA IC design/modeling tools to enable simulation/emulation, physical verification, parasitic extraction, and 3D heterogenous integrated (3DHI) modeling.
  • Help develop, deploy, and maintain TIE's Assembly Design Kits (ADKs).
  • Maintain interoperability and compatibility of TIE’s design kits with partner process design kits (PDKs), internal PDKs and ADKs, and vendor EDA tool revisions.
  • Develop innovative physical design place and route methodology and flow solutions to meet current and future design challenges.
  • Help establish and validate physical design methodologies, flow automation and infrastructure for internal 3D heterogenous micro-system modeling teams.
  • Automation of test structure layouts to drive next generation processing capabilities across a wide range of materials.
  • Support TIE's standard cell offerings and drive validation/simulation/emulation capability around those standard cells.
  • Facilitate and oversee project tapeouts.
  • Providing technical leadership, mentoring and customer support for internal design and 3D modeling teams.
Desired Qualifications
  • Master’s or advanced degree in semiconductor engineering fields such as Electrical Engineering, Computer Science, or other relevant disciplines.
  • Previous experience in setting up and facilitating Design environments and maintaining design kit operability and coordination for cross functional design, modeling, and/or layout teams.
  • Previous experience integrating PDK and/or ADKs to enable 2.5D or 3D Systems on Chips.
  • Experience evaluating EDA tool capabilities driving EDA vendors to make tool improvements or enable new functions to meet advanced or unique design requirements.
  • Experience in a startup or research and development (R&D) environment.
University of Texas at Austin

University of Texas at Austin

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