Responsibilities

• Lead functional and performance verification of the load store unit for a from-scratch high performance CPU while working closely with Architecture and RTL team 
• Develop detailed block level verification plans for load store that includes both architectural (RISCV ISA) and microarchitectural functionality 
• Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers 
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain 
• Evaluate and integrate open-source toolchains into the DV flow 
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon 
• Work with design, test and post silicon validation teams to ensure high quality delivery of the load store block 

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience 
• Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem  
• Experience working on an x86, ARM or RISCV based CPU 
• Architectural understanding of address translation, memory ordering, cache cohereney protocols, memory consistency and multi-processors 
• Significant experience debugging RTL and DV in a simulation environment 
• Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools 
• Experience with C++ / SV / UVM as well as scripting languages 
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator) 
• Strong problem solving and debug skills across various levels of design hierarchies