Lead CPU Load/Store Verification Engineer

Updated on 5/24/2023

Locations

Austin, TX, USA

Experience Level

Entry

Junior

Mid

Senior

Expert

Requirements

BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
Experience working on an x86, ARM or RISCV based CPU
Architectural understanding of address translation, memory ordering, cache cohereney protocols, memory consistency and multi-processors
Significant experience debugging RTL and DV in a simulation environment
Verification methodologies and techniques - Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
Experience with C++ / SV / UVM as well as scripting languages
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

Lead functional and performance verification of the load store unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
Develop detailed block level verification plans for load store that includes both architectural (RISCV ISA) and microarchitectural functionality
Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Evaluate and integrate open-source toolchains into the DV flow
Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
Work with design, test and post silicon validation teams to ensure high quality delivery of the load store block

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Technical lead focused on Load Store verification for high-performance CPUs. The person coming into this role will help define the overall load store verification strategy, lead the DV plan and execution for this domain.

Responsibilities

Lead functional and performance verification of the load store unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
Develop detailed block level verification plans for load store that includes both architectural (RISCV ISA) and microarchitectural functionality
Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
Evaluate and integrate open-source toolchains into the DV flow
Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
Work with design, test and post silicon validation teams to ensure high quality delivery of the load store block

Experience & Qualifications

BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
Experience working on an x86, ARM or RISCV based CPU
Architectural understanding of address translation, memory ordering, cache cohereney protocols, memory consistency and multi-processors
Significant experience debugging RTL and DV in a simulation environment
Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
Experience with C++ / SV / UVM as well as scripting languages
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies

Multiple geographies: Austin, Santa Clara

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

51-200 employees

Website

Computer processor architecture manufacturer

Company Overview

Tenstorrent is on a mission to address the rapidly growing compute demands for software 2.0. The company designs processors that are optimized for neural network inference, training and can also execute other types of parallel computation.

Company Core Values

Collaboration
Curiosity
Commitment to solving hard problems