Full-Time

Senior Pcie/CXL Electrical Validation Engineer

Astera Labs

Astera Labs

201-500 employees

Semiconductor-based connectivity solutions for cloud-scale data

Hardware

Senior

Santa Clara, CA, USA

Required Skills
Git
Requirements
  • Strong academic and technical background in Electrical or Computer Engineering
  • ≥5 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
  • Familiarity with PCIe and CXL specs, especially Electrical Compliance sections
  • Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ
  • Experience in system testing, characterization, margin analysis and optimization of high-speed PCIe/CXL data links over long and short channels
  • Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
  • Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis
  • Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA
Responsibilities
  • Develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions
  • Formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness

Company Stage

N/A

Total Funding

$739.4M

Headquarters

Santa Clara, California

Founded

2017

Growth & Insights
Headcount

6 month growth

22%

1 year growth

44%

2 year growth

149%