Full-Time

Process Engineer

Updated on 8/23/2026

Substrate

Substrate

11-50 employees

Develops advanced X-ray lithography chipmaking system

Compensation Overview

$150k - $250k/yr

No H1B Sponsorship

San Francisco, CA, USA

Remote

Several days per week required at user facilities around the San Francisco Bay Area; travel beyond the Bay Area may be required.

Bachelor's

Category
Process Engineering
Required Skills
Process Engineering
Data Analysis

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Requirements
  • At least 3 years of hands-on micro- or nanofabrication experience in cleanroom user facilities.
  • Demonstrated ability to work safely and collaboratively in a cleanroom user facility.
  • Willingness and ability to work in several user facilities around the San Francisco Bay Area several days per week.
  • Demonstrated experience handling delicate samples and operating complex fabrication and characterization equipment.
  • Fundamental understanding of micro- and nanofabrication considerations such as top-down versus bottom-up approaches, pattern transfer, material compatibilities, etch selectivity and directionality, and thin-film and surface engineering.
  • Understanding of the mechanical, optical, and chemical properties of materials that determine the performance of nanofabricated devices.
  • Strong written and oral communication skills, attention to detail, and organizational skills.
  • Ability to solve complex design challenges independently and as part of a team.
  • Ability to collaborate with a large and multidisciplinary technical group.
  • B.S. or higher degree in chemical engineering, electrical engineering, materials science, mechanical engineering, physics, or a related discipline in the physical or engineering sciences.
  • Applicants must be legally authorized to work in the United States.
Responsibilities
  • Collaborate closely with the technical team to conceptualize, design, prototype, and characterize nanofabricated optical devices.
  • Fabricate MEMS/NEMS devices using photo- and electron-beam lithography, thin-film deposition, and wet and dry etching in user facilities.
  • Iterate structural designs and tune lithography, deposition, and etch parameters to optimize processes and improve performance.
  • Perform mechanical, optical, and chemical characterization of thin films using profilometry, ellipsometry, and X-ray photoelectron spectroscopy.
  • Characterize pattern fidelity and resolution using scanning electron microscopy and atomic force microscopy.
  • Contribute to fabrication strategies, including process-flow design, material-compatibility studies, and mask-layout computer-aided design.
  • Contribute to characterization strategies for bulk materials, nanopatterned structures, and thin films to study the mechanical, chemical, and optical properties driving device performance.
  • Design, coordinate, and conduct experiments in various user facilities.
  • Contribute to the build-up and installation of internal research facilities.
  • Record, process, and interpret data and results for the wider team.
Desired Qualifications
  • At least 3 years of hands-on experience with characterization techniques such as electron microscopy and scanning probe microscopy.
  • Experience operating a Raith EBPG 5200/5200+, including aligned exposures.
  • At least 1 year of hands-on experience with inductively coupled plasma etching, with a strong understanding of plasma-etching principles and recipe parameters.
  • Experience in industrial research and development.
  • Experience with instrument scoping, procurement, installation, and commissioning.
  • Experience with safety procedures and best practices when working with potentially hazardous liquid chemicals.

Substrate is developing a new chipmaking system that uses X-ray lithography powered by a proprietary particle accelerator to pattern circuits on silicon wafers. The technology aims to lower lithography costs by about half and is demonstrated at U.S. National Laboratories and in its own facilities. It differentiates itself by pursuing a more vertically integrated U.S. foundry to reduce reliance on overseas fabrication and strengthen supply-chain resilience. The goal is to produce its first chips by 2028 and help bring advanced AI and robotics chips manufacturing back to the United States.

Company Size

11-50

Company Stage

Late Stage VC

Total Funding

$100M

Headquarters

San Francisco, California

Founded

2022

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Simplify Jobs

Simplify's Take

What believers are saying

  • Substrate's April 2026 narrative stayed visible on substrate.com, signaling active investor and talent attention.
  • In-Q-Tel backing gives Washington-aligned credibility for defense and supply-chain resilience work.
  • Process Engineer hiring in February 2026 shows continued buildout of internal research facilities.

What critics are saying

  • Substrate still shows no shipped chips, and 2028 remains its first-chip target.
  • ASML and TSMC keep advancing; TSMC rejected High-NA EUV purchases in April 2026.
  • If X-ray lithography misses throughput or yield, Substrate becomes an expensive physics demo.

What makes Substrate unique

  • James Proud's 2022-founded team is building X-ray lithography to challenge ASML directly.
  • Substrate raised $100 million in 2025-2026 from Founders Fund, General Catalyst, and In-Q-Tel.
  • It targets vertically integrated foundries, not just tooling, aiming to own wafer economics.

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Benefits

Health Insurance

Dental Insurance

Vision Insurance

Life Insurance

Disability Insurance

Health Savings Account/Flexible Spending Account

Unlimited Paid Time Off

Flexible Work Hours

Remote Work Options

Paid Vacation

Paid Sick Leave

Paid Holidays

Hybrid Work Options

Stock Options

401(k) Retirement Plan

Wellness Program

Mental Health Support

Gym Membership

Phone/Internet Stipend

Home Office Stipend

Corporate Social Events

Growth & Insights and Company News

Headcount

6 month growth

0%

1 year growth

0%

2 year growth

0%
Financial Times
Oct 28th, 2025
Silicon Valley chip start-up raises $100mn to take on TSMC and ASML

Substrate plans to use particle accelerators to lower cost of chip manufacturing