Full-Time
Emulation Engineer
Posted on 5/1/2024
Semiconductor connectivity solutions for AI and cloud
Hardware
Mid
Santa Clara, CA, USA
Required Skills
Verilog
Python
Perl
Requirements
- Strong academic and technical background in computer/electrical engineering
- Bachelor’s in EE or Computer Science required, Master’s preferred
- ≥3 years’ experience supporting or developing complex SoC/silicon products
- Experience with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs
- Professional attitude with the ability to prioritize tasks and work with minimal guidance
- Authorized to work in the US and start immediately
- Experience with emulation and prototyping technologies like Palladium/Zebu/Veloce or Protium/EP/HAPS
- Strong software skills in C/C++ for emulation
- Experience with System Verilog
- Experience in programming and scripting languages like python/perl
- Currently based locally or open to relocation
Responsibilities
- Contribute to ASIC bringup, architectural validation, performance testing
- Drive SW architectural changes
- Understand software and hardware co-simulation approaches and debug methods
- Modeling for emulation and prototyping
- Debugging SW/FW/bus protocols using emulation
- Work with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs
Astera Labs specializes in semiconductor-based connectivity solutions, including PCIe, CXL, and Ethernet technologies, designed to optimize cloud and AI infrastructure by addressing performance bottlenecks in data-centric systems. Their purpose-built products enable high-bandwidth, low-latency interconnects for compute, storage, and accelerator resources, as well as robust CXL and PCIe connectivity for GPUs, AI accelerators, and networking applications.
Company Stage
IPO
Total Funding
$739.4M
Headquarters
Santa Clara, California
Founded
2017
Growth & Insights
Headcount