d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models.The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.  

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: CAD STA Engineer, Principal

What you will do:

As part of this engineering team, you will be responsible for the methodology & flow development of Physical Design and Timing Closure for custom and semi-custom blocks. You will develop CAD tools for optimization of Synthesis, Floorplan, Place and Route and Design closure. You will develop automation scripts for Design, Verification including regression runs. You will develop methodology and flows with revision control systems such as git. You will also be interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirements.

What you will bring:

Minimum:

• MS in EE/CS with 15+ years of previous experience.

• Experience with scripting/programming using Tcl/Tk/Perl/Python/SKILL.

• Exposure on ASIC design, layout and semiconductor device/process through previous work/intern experience or course work.

• Detail oriented, self-motivated team worker, good verbal, and written communication skills.

• Knowledge of Synopsys/Cadence P&R tools.

• Passionate about thriving in a fast-paced and dynamic startup culture.

Preferred:

• Previous experience on physical design and automatic place and route.

• Exposure to Circuit Schematic and Layout tools.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.