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Physical Design Verification Engineer – Principal
Confirmed live in the last 24 hours
Santa Clara, CA, USA
Experience Level
  • Minimum 7 years of relevant experience
  • Background with FinFets and double exposure metallization is highly desired
  • Familiarity with Cadence and Mentor tools is required
  • Shell, Skill, Calibre and other programming knowledge
  • Familiarity with Physical Verification flow automation
  • Familiar in identifying and addressing issues often found at the chip level, some of which include:
  • Density
  • Latch up triggered failures
  • Abutment conflicts
  • Data integrity
  • Short isolation and open/swapped nets
  • BS / MS in EE/CSE
  • Responsibilities include partition and chip-level level ownership of physical design verification (PDV), and physical design reviews
  • Execute and debug final verification flows in preparation for gds tape out delivery (DRC, LVS, DFM, Antenna, Density Fill Routines, XOR, etc.)
  • LVS / DRC check coding
  • Support all PDV sign-off scripts at partition and at chip-level
  • Support on metal-fill and density check for all partitions and at the chip-level
  • Support on DRC fixes for FinFet designs
  • Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam
Ampere is a semi-conductor company.
Company Overview
Ampere is a semi-conductor company.