Multi-Chiplet Fabric Performance Engineer

Requirements

• Knowledge of on-chip interconnection networks (NoC) including routing, arbitration, deadlock-avoidance and flow control methods.
• Experience in developing and working with interconnect-only as well as full-system simulators.
• Cycle accurate performance modeling experience using C/C++.
• Analytical modeling for fabric components with focus on latency and bandwidth.
• Ability to work well in a team and be productive under aggressive schedules.
• Proficiency in C or C++, Python and System Verilog.
• Experience with high-level simulators for power estimation is a plus.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.

Responsibilities

• Work closely with fabric architects and micro-architects to define the multi-chiplet interconnection solution for Data Parallel Accelerator.
• Ability to represent key design details in a Python-based analytical model for peak bandwidth estimation under different traffic scenarios.
• Ability to represent architectural and micro-architectural details in cycle accurate performance models and setup performance / design space exploration studies using those models.
• Bringup and performance debug for multi-chiplet configs including full system compute and on-chip fabrics.
• Performance correlation of model with RTL - explore high performance strategies and validate that the RTL design meets targeted performance
• Develop performance verification tests to ensure quality of model and design.