Senior Principal Digital Design Engineer
Posted on 3/31/2024
Astera Labs

201-500 employees

Semiconductor-based connectivity solutions for cloud-scale data
Company Overview
Astera Labs stands at the forefront of semiconductor-based connectivity solutions, specializing in the optimization of accelerated computing platforms for AI applications. Their pioneering products, based on PCIe, CXL, and Ethernet technologies, address the growing demand for efficient data processing, transfer, and storage in today's data centers. With a focus on enabling intelligent data infrastructure at cloud-scale, Astera Labs is a key player in supporting the vast majority of organizations investing in big data and AI initiatives.
Hardware

Company Stage

N/A

Total Funding

$739.4M

Founded

2017

Headquarters

Santa Clara, California

Growth & Insights
Headcount

6 month growth

23%

1 year growth

45%

2 year growth

151%
Locations
Santa Clara, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Python
CategoriesNew
Hardware Engineering
Computer Hardware Engineering
Electronic Hardware Engineering
Requirements
  • Bachelor's degree in EE
  • Master's degree in EE
  • 12+ years' experience in SoC/silicon products
  • Strong knowledge of high-speed protocols like PCIe, Ethernet, NVMe, etc.
  • Experience with Cadence and/or Synopsys digital design tools/flows
  • Familiarity with UVM based design verification
  • Scripting with Python or other equivalent programming languages
  • Authorized to work in the US
Responsibilities
  • Developing micro-architecture and implementation of front-end circuit design
  • RTL, synthesis, IP integration, and block-level verification for high performance network controllers
  • Driving multiple complex designs to production
  • Silicon bring-up and debug expertise