Responsibilities

• Define architecture and microarchitecture for memory subsystem components including cache, interconnects and memory.
• Work with architecture and design teams to develop performance models in C++ for design space exploration and provide feedback to architecture and design teams.
• Validate the performance model against the specification and correlate with RTL.
• Plan and analyze results of performance studies analyzing micro-architectural proposals.
• Develop performance verification tests to ensure quality of model and design.

Requirements

• Strong knowledge in SoC architecture and power/performance trade-offs.
• Proficient at SW programming with good understanding of C/C++, Python, and modular object oriented software development.
• Experience in simulators for perf model development and perf analysis. Experience in different modeling techniques from analytical, event driven and cycle accurate.
• In-depth knowledge of memory subsystem architecture, microarchitecture and design including caches, cache coherency, NOC, LPDDR/DDR/HBM, and IO.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Knowledge of SystemVerilog and waveform debugging tools is a plus.
• Ability to work collaboratively in a team and be productive under aggressive schedules.

Education and Experience

• Bachelor’s degree plus 5 years of industry experience.
• Master’s degree plus 3 years of industry experience.
• Ph.D with internship experience.