Full-Time
Applications/Validation Engineer
Rambus
1,001-5,000 employees
Licenses high-speed chip-to-chip connectivity IP
No salary listed
San Jose, CA, USA
Hybrid
Hybrid schedule with an average of at least three days onsite per week; international travel to customer sites may be required.
Bachelor's, Master's
 Hardware Engineering (1) |
|---|
Get referred to Rambus
See people who can refer or advise you
- Experience with DRAM and failure analysis.
- Familiarity with DDR4 and DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers.
- Understanding of signal integrity issues at clock rates of 3 GHz and above.
- Experience with power management and I2C/I3C serial interfaces.
- Extensive experience probing with high-speed oscilloscopes and other laboratory equipment.
- Experience using fundamental root-cause techniques, including fishbone analysis and design of experiments, to solve complex problems.
- Ability to read and modify MRC BIOS code and use server-platform debug tools from Intel or AMD.
- Ability to use scripting languages such as Perl, Tcl, or Python to analyze data-log text files and automate system and bench testing.
- Ability to travel to customer sites, including internationally.
- Excellent verbal and written communication skills in English and Korean.
- A BS degree or higher in Electrical Engineering or a related field.
- Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion.
- Support technical qualification of new chip designs to secure customer design wins.
- Assist with validation and debugging of new memory interface chips for DDR5 servers.
- Collect and analyze system-level signal-integrity data.
- Conduct failure analysis and prepare failure-analysis and 8D reports.
- Gather customer technical feedback and communicate it to Marketing and Engineering teams.
- Present technical updates to customers and company management in writing and verbally through quality presentations.
- Prepare technical documentation such as datasheets, user guides, and application notes.
- Good understanding of ATE tester operation.
Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.
Company Size
1,001-5,000
Company Stage
IPO
Headquarters
San Jose, California
Founded
1990
Get referred to Rambus
See people who can refer or advise you
Simplify's Take
What believers are saying
- Q2 2026 revenue reached $207.4 million, up 20%, and Q3 guidance rose again.
- Rambus launched PCIe 7.0 switch IP on May 5, 2026, targeting AI infrastructure.
- A Tier-1 hyperscaler chose Rambus next-generation HBM IP, validating its licensing model.
What critics are saying
- Rambus shares fell 19.8% after Q2 2026, signaling fragile investor confidence.
- MRDIMM contributes minimally in Q4 2026, delaying a meaningful ramp until 2027.
- If memory OEMs internalize interface IP, Rambus loses its licensing core.
What makes Rambus unique
- Rambus monetizes memory and security IP without fabs, keeping margins asset-light.
- Its DDR5 RCD, PMIC, and HBM IP spans server, AI, and automotive designs.
- RT-648 embeds Arm-based root-of-trust security into automotive SoCs with Telechips deployment.
Help us improve and share your feedback! Did you find this helpful?
Benefits
Health Insurance
Dental Insurance
Vision Insurance
401(k) Retirement Plan
401(k) Company Match
Flexible Work Hours
Hybrid Work Options
Paid Vacation
Gym Membership
Growth & Insights and Company News
6 month growth
↑ 2%1 year growth
↑ 2%2 year growth
↑ 2%TSMC OIP Ecosystem Forum North America. Event details. Rambus is excited to be participating at TSMC OIP Ecosystem Forum North America! Stop by booth #407 to chat with its experts about its solutions. Nidish Kamath, Director of Product Management, will also be presenting on LPDDR Memory. See session information below: Title: LPDDR Memory: Enabling Power-Efficient Performance in AI, Automotive and Data Center Systems Speaker: Nidish Kamath Time: 4:10pm- 4:30pm Abstract: The rapid growth of AI, edge computing, and mobile-class compute in data center, automotive, and client platforms is fundamentally changing memory subsystem requirements. While performance demands continue to increase - driven by AI inference, real-time analytics, and always-on workloads - power efficiency and form-factor constraints are becoming equally critical. Traditional high-performance memory solutions often struggle to meet aggressive power budgets, while mobile-oriented memory technologies must now scale to support higher bandwidths and more complex system architectures. LPDDR has emerged as a key enabler for these new compute paradigms, extending beyond smartphones into AI accelerators, automotive SoCs, and power-constrained data center applications. However, adopting LPDDR at scale introduces several challenges, including higher interface speeds, tighter signal integrity margins, increased controller and PHY complexity, and the need for robust power management and reliability features. Additionally, advanced process nodes exacerbate variability and noise sensitivity, requiring closer co-optimization between memory IP, silicon technology, and system design. As LPDDR continues to evolve with higher data rates, lower operating voltages, and new architectural features, designers need proven, scalable solutions that balance performance, power, and reliability while enabling faster time-to-market.
SEMICON(R) India 2026. Event details. Rambus is excited to be participating in SEMICON(R) India 2026! Stop by and meet its experts to learn more about its Silicon IP solutions. Company. Products. Markets.
Rambus reported second-quarter 2026 revenue of $207.39 million and net income of $67.61 million, alongside completion of a multi-year share repurchase programme totalling 14,484,994 shares for $466.93 million. The company launched DDR5 9600 chipsets and secured a next-generation HBM IP design win with a Tier-1 US hyperscaler. It guided third-quarter revenue to $210 million to $216 million and GAAP diluted EPS of $0.59 to $0.67. Despite record results, the stock fell 19.8%. Analysts remain divided on the company's prospects, with the most optimistic projecting earnings could reach $480 million, whilst others caution that supply constraints or platform delays could limit upside. The investment case hinges on continued demand for high-speed, AI-centric memory solutions offsetting concentration risks in key product lines.
Rambus Inc. reported record quarterly revenue of $207.4 million in Q2 2026, marking the first time the company surpassed the $200 million threshold. Product revenue grew 22% year-over-year, driven by leadership in DDR5 RCDs and increasing adoption across AI and traditional server environments. The company attributed growth to the shift in AI workloads toward inference and agentic use cases requiring more memory-intensive infrastructure. Management expects double-digit product revenue growth to continue in Q3, with a sequential increase of 14% at the midpoint. Rambus announced a design win with a Tier 1 US hyperscaler for next-generation HBM in future AI chips. The Silicon IP business is projected to grow 10% to 15% annually. Strategic focus for 2027 includes Gen 5 DDR5 growth and initial contributions from MRDIMM architectures.
Rambus reported record second-quarter fiscal 2026 revenue of $207.4 million, up 20% year-over-year and 15% sequentially, marking the first time revenue surpassed $200 million. Non-GAAP net income reached $84.4 million, or $0.77 per diluted share, growing 24% year-over-year and 21% sequentially. Product revenue hit a record $99.2 million, driven by the company's DDR5 registered clock driver business. Royalties revenue totalled $84.2 million, whilst contract and other revenue was $24 million, primarily from silicon IP. Chief executive Luc Seraphin attributed growth to AI infrastructure demand, CPU-based servers and rising memory requirements. The company introduced DDR5 9600 chipsets during the quarter and is developing new memory-module architectures including MRDIMM and LPDDR5X SOCAMM2.