Standard Cell Library Engineer
Posted on 4/27/2022
San Jose, CA, USA
- Minimum Qualifications:You must possess a minimum of Bachelor's degree or Master's degree in the field of electronics engineering.Specialization or experience in VLSI is preferred.Preferred Qualifications:A minimum of 2+ years of relevant experience in standard cell library design.The successful candidate must possess excellent written and verbal communication skills, solid customer/result orientation and the willingness to work with external and internal partners in a flexible manner
- Design and implementation of the combinatorial, clock, power management and sequential circuits for Intel's newest process technologies
- Parasitic extraction and circuit optimization for power/performance/robustness/density
- Library characterization for timing, noise, power and variation models (non-linear delay models and composite current source models, parametric on chip variation models)
- Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. APL characterization and modeling
- Developing functional models behavioral Verilog, power udp Verilog and fault models
- Development of automation for library modeling, validation, quality checking, performance and reliability verification
- The library build, validation, QA, release, and support
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