Responsibilities

• Work closely with other PD engineers and the front end team to understand the chip architecture and drive physical design considerations early in the project cycle
• Physical design tasks such as synthesis, PnR, timing closure, area improvement, floor-planning, clocking, I/O planning and power optimization
• Learn and implement end-to-end flow development, synthesis to sign off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Some experience with synthesis, place and route flows and tools
• Basic familiarity with timing, EM/IR, and power analysis tools
• Knowledge of low-power design techniques such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Good understanding of logic design fundamentals and gate/transistor level implementation
• Strong problem-solving skills