Lead Debug and Trace Design Verification Engineer
Posted on 12/30/2022
INACTIVE
Tenstorrent

51-200 employees

Computer processor architecture manufacturer
Company Overview
Tenstorrent is on a mission to address the rapidly growing compute demands for software 2.0. The company designs processors that are optimized for neural network inference, training and can also execute other types of parallel computation.
Locations
Austin, TX, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
C/C++
Verilog
VHDL
CategoriesNew
Electrical Engineering
Hardware Engineering
Requirements
  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  • Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
  • Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
  • Verification methodologies and techniques - Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
  • Experience with C++ / SV / UVM as well as scripting languages
  • Experience with assembly level programming
  • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
  • Strong problem solving and debug skills across various levels of design hierarchies RISCV, Debug and Trace Verification Engineer
Responsibilities
  • Define design for Debug requirements for a from-scratch high performance CPU working closely with Architecture and RTL team
  • Develop detailed verification plans for debug and trace logic for a server class CPU based on RISCV ISA
  • Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers
  • Develop stimulus that spans pre-silicon, emulation and post-silicon domain
  • Evaluate and integrate open-source toolchains into the DV flow
  • Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
  • Work with design, test and post silicon validation teams to deploy debug features