Lead Debug and Trace Design Verification Engineer @ Tenstorrent

INACTIVE

Full-Time

Lead Debug and Trace Design Verification Engineer

Tenstorrent

201-500 employees

Builds next-generation computers for AI applications

Hardware

AI & Machine Learning

Senior

Austin, TX, USA

Required Skills

Verilog

VHDL

C/C++

Requirements

BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
Verification methodologies and techniques - Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
Experience with C++ / SV / UVM as well as scripting languages
Experience with assembly level programming
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies RISCV, Debug and Trace Verification Engineer

Responsibilities

Define design for Debug requirements for a from-scratch high performance CPU working closely with Architecture and RTL team
Develop detailed verification plans for debug and trace logic for a server class CPU based on RISCV ISA
Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers
Develop stimulus that spans pre-silicon, emulation and post-silicon domain
Evaluate and integrate open-source toolchains into the DV flow
Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
Work with design, test and post silicon validation teams to deploy debug features

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Verification architect focused on Debug and Trace Logic for high-performance CPUs. The person

coming into this role will help define the overall design for debug strategy, lead the DV plan and

execution for this domain.

Responsibilities

Define design for Debug requirements for a from-scratch high performance CPU working closely with Architecture and RTL team
Develop detailed verification plans for debug and trace logic for a server class CPU based on RISCV ISA
Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers
Develop stimulus that spans pre-silicon, emulation and post-silicon domain
Evaluate and integrate open-source toolchains into the DV flow
Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
Work with design, test and post silicon validation teams to deploy debug features

Experience & Qualifications

BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
Experience with C++ / SV / UVM as well as scripting languages
Experience with assembly level programming
Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Strong problem solving and debug skills across various levels of design hierarchies RISCV, Debug and Trace Verification Engineer

Location:

We have presence in Toronto (CAN), Austin, Santa Clara, Portland, Boston, and Raleigh (US), as well as Bangalore (India), and Cambridge (UK). We are open to remote candidates on a case by case basis.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

Tenstorrent

View

Website

View Company Profile

Tenstorrent, a global leader in AI computing, offers a unique work environment that fosters collaboration among experts in computer architecture, ASIC design, advanced systems, and neural network compilers. The company's competitive edge lies in its scalable RISC-V design, a testament to its commitment to technical innovation. With a diverse and inclusive culture spread across offices in Canada, the U.S., Belgrade, and Bangalore, Tenstorrent provides ample opportunities for growth and learning in the rapidly evolving AI industry.

Company Stage

Series C

Total Funding

$334.5M

Headquarters

Toronto, Canada

Founded

2016

Growth & Insights

Headcount

6 month growth

↑ 21%

1 year growth

↑ 72%

2 year growth

↑ 173%

INACTIVE