Compensation Overview

Job Description/Responsibilities

The successful candidate will own testability of the core fabric of high-performance standalone and embedded FPGAs. Responsibilities include the following:

• Develop flows to automate fault testing of the FPGA core fabric
• Work actively with frontend and backend designers to support DFT implementation
• Work with test and product engineers to prepare ATE test patterns and support the test program from wafer sort to final test
• Provide support to customers on the testability of Achronix eFPGA products
• Mentor junior engineers

Skills and Qualifications

• Experience programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch
• Experience designing/maintaining flows and methodologies from scratch
• Experience with digital VLSI design and verification
• Experience reading and writing RTL (e.g., Verilog)
• Experience with industry standard DFT flows (ATPG, BIST, etc.), fault coverage and fault analysis is a plus
• Familiarity with using and/or designing FPGAs is a plus
• Excellent problem solving and debugging skills
• Extremely well organized and excellent communication skills
• BS/MS in Electrical Engineering or Computer Science plus 2–10 years experience

The compensation range for this position is $160,000 - $180,000. Salary ranges dependent on experience and location.