FPGA Test Automation Engineer
Confirmed live in the last 24 hours
Achronix Semiconductor

51-200 employees

Provides high-performance FPGA solutions and accelerator cards
Company Overview
Achronix Semiconductor Corporation, a fabless semiconductor company based in Santa Clara, stands out for its unique offering of both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions, a combination not found in any other supplier. The company's products, including the VectorPath® Accelerator Card that supports PCIe Gen 5.0 and 400 GbE interfaces, are designed to meet the high-performance needs of AI, ML, networking, and data center applications. Achronix further distinguishes itself with its best-in-class EDA software tools, ensuring robust support for all its products.
Hardware

Company Stage

Series C

Total Funding

$288.2M

Founded

2004

Headquarters

Santa Clara, California

Growth & Insights
Headcount

6 month growth

1%

1 year growth

-1%

2 year growth

21%
Locations
Santa Clara, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Verilog
Python
Perl
FPGA
CategoriesNew
Hardware Engineering
Requirements
  • Experience programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch
  • Experience designing/maintaining flows and methodologies from scratch
  • Experience with digital VLSI design and verification
  • Experience reading and writing RTL (e.g., Verilog)
  • Excellent problem solving and debugging skills
  • Extremely well organized and excellent communication skills
  • BS/MS in Electrical Engineering or Computer Science plus 2-10 years experience
Responsibilities
  • Develop flows to automate fault testing of the FPGA core fabric
  • Work actively with frontend and backend designers to support DFT implementation
  • Work with test and product engineers to prepare ATE test patterns and support the test program from wafer sort to final test
  • Provide support to customers on the testability of Achronix eFPGA products
  • Mentor junior engineers
Desired Qualifications
  • Experience with industry standard DFT flows (ATPG, BIST, etc.), fault coverage and fault analysis is a plus
  • Familiarity with using and/or designing FPGAs is a plus