Lead Debug and Trace RTL Engineer @ Tenstorrent

Lead Debug and Trace RTL Engineer

Posted on 12/30/2022

INACTIVE

51-200 employees

Computer processor architecture manufacturer

Company Overview

Tenstorrent is on a mission to address the rapidly growing compute demands for software 2.0. The company designs processors that are optimized for neural network inference, training and can also execute other types of parallel computation.

Locations

Austin, TX, USA

Experience Level

Entry

Junior

Mid

Senior

Expert

Requirements

BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Expertise in microarchitecture definition and specification development
Prior experience in industry standard ISAs - ARM, RISC-V, X86 preferred
Strong problem solving and debug skills across various levels of design hierarchies

Responsibilities

Define design for Debug requirements for a from-scratch high performance and architect the overall debug capabilities and infrastructure
Develop detailed microarchitecture for debug and trace logic for a server class CPU based on RISCV ISA
RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
Work with design, test and post silicon validation teams to deploy debug features
Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
Enhance RTL design environment, tools and infrastructure

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Microarchitecture and RTL Design focused on Debug and Trace Logic for high-performance CPUs. The person coming into this role will help define the overall design for debug strategy, lead the microarchitecture and RTL development for this domain.

Responsibilities

Define design for Debug requirements for a from-scratch high performance and architect the overall debug capabilities and infrastructure
Develop detailed microarchitecture for debug and trace logic for a server class CPU based on RISCV ISA
RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
Work with design, test and post silicon validation teams to deploy debug features
Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
Enhance RTL design environment, tools and infrastructure

Experience & Qualifications

BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
Expertise in microarchitecture definition and specification development
Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
Strong problem solving and debug skills across various levels of design hierarchies

Location:

We have presence in Toronto (CAN), Austin, Santa Clara, Portland, Boston, and Raleigh (US), as well as Bangalore (India), and Cambridge (UK). We are open to remote candidates on a case by case basis.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.