Job Details:

Job Description: 

Role and Responsibilities:

As a member of E-core CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel’s compute roadmap.

As a core IP Physical Design Engineer your responsibilities include:

• Synthesis and Place and Route using industry standard tools for high speed CPU core design.
• Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.
• Develop strategies to deliver reproducible design convergence results.
• Help to create and refine synthesis flow for the project team.
• Develop and recommend better design method practices to enable better synthesis convergence.

The ideal candidate will exhibit behavioral traits that demonstrate:

• Willingness to work with others in a highly complex decision space.
• Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule.
• Excellent verbal and written communication and collaboration skills.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelors in Computer Engineering or Electrical Engineering or related technical field with 1+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related technical field.

Experience in:

• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
• PV convergence (including static timing and power analysis).
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby).
• Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP.

Preferred Qualifications:

• Industry experience/exposure with CPU Micro-Architecture
• Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
• Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques
• Strong knowledge of RTL to GDS methodologies and formal equivalence
• Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.