Full-Time

Firmware Engineer

Ddr

Posted on 5/30/2024

Astera Labs

Astera Labs

201-500 employees

Semiconductor connectivity solutions for AI and cloud

Hardware

Senior

Vancouver, BC, Canada

Required Skills
Git
Requirements
  • Bachelor’s degree in electrical engineering / Electronics / Computer Science or related fields.
  • Professional attitude with the ability to prioritize/estimate tasks and to work with minimal guidance and supervision.
  • Proven track record solving problems independently and working with others in DDR development.
  • 5+ years of experience in developing firmware using C/C++ in Embedded environments.
  • 3+ years of DDR training and/or DDR controller features including Memory RAS for (LP)DDR4/DDR5/HBM.
  • Good knowledge of DDR controllers at PHY transaction level.
  • Familiarity with DDR memory standards and experience in system testing, characterization, margin analysis and optimization.
  • Ability to design, implement, and write unit-level tests for DDR features.
  • Working knowledge of software build environments, gcc/make.
  • Experience with developer workflows, SCM (preferably git), code reviews, CI.
Responsibilities
  • Designing and developing Firmware for enabling technologies like DDR and/or CXL/PCIe for future-looking products.
  • Implementing major differentiating features of Astera Labs’ products through firmware.
  • Being customer-facing to ensure customer needs are fully comprehended.
  • Post-silicon bring-up and tuning of single/multi-rank DDR memory interfaces.
  • Working with DRAM memory vendors on (LP)DDR4/5 to identify issues and improve memory calibration and tuning sequences.
  • Conducting system testing, characterization, margin analysis, and optimization.
  • Designing unit-level tests for DDR features.
  • Participating in software build environments, developer workflows, SCM, code reviews, CI.
  • Measuring high-speed interfaces (PCIe, DDR, 25/50G/100G SerDes).
  • Server memory performance tuning for latency and bandwidth.

Astera Labs specializes in semiconductor-based connectivity solutions, including PCIe, CXL, and Ethernet technologies, designed to optimize cloud and AI infrastructure by addressing performance bottlenecks in data-centric systems. Their purpose-built products enable high-bandwidth, low-latency interconnects for compute, storage, and accelerator resources, as well as robust CXL and PCIe connectivity for GPUs, AI accelerators, and networking applications.

Company Stage

IPO

Total Funding

$739.4M

Headquarters

Santa Clara, California

Founded

2017

Growth & Insights
Headcount

6 month growth

28%

1 year growth

50%

2 year growth

140%
INACTIVE