Job Description:

As an Astera Labs Firmware Engineer, you will be designing and developing Firmware for enabling technologies like DDR and/or CXL/PCIe for future-looking products defined by Astera Labs CXL solutions. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. 

Multiple levels for this role are being considered and will be based on the candidate’s experience.

Basic qualifications:

• Bachelor’s degree in electrical engineering / Electronics / Computer Science or related fields.
• Professional attitude with the ability to prioritize/estimate tasks and to work with minimal guidance and supervision.
• Proven track record solving problems independently and working with others in DDR development.

Required experience:

• 5+ years of experience in developing firmware using C/C++ in Embedded environments.
• 3+ years of DDR training and/or DDR controller features including Memory RAS for (LP)DDR4/DDR5/HBM -and/or-
• Good knowledge of DDR controllers at PHY transaction level.
• Familiarity with DDR memory standards and experience in system testing, characterization, margin analysis and optimization
• Ability to design, implement, and write unit-level tests for DDR features.
• Working knowledge of software build environments, gcc/make.
• Experience with developer workflows, SCM (preferably git), code reviews, CI.

Preferred experience:

• Post-silicon bring-up and tuning of single/multi-rank DDR memory interfaces.
• Experience working with DRAM memory vendors on (LP)DDR4/5 to identify issues and working with internal SoC HW/FW teams to improve memory calibration and tuning sequences.
• Knowledge of memory subsystem compliance including data integrity and RAS is a plus.
• Experience in advanced features of DDR like ECS/PPR/Chip Kill, device configuration, and error handling.
• Experience with measurements of high-speed interfaces (PCIe, DDR, 25/50G/100G SerDes).
• Knowledge of server memory performance tuning for latency and bandwidth.

The base salary range is CAD 140,000.00 – CAD 240,000.00 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.