Member of Technical Staff Ref @ Rivos

Verify the microarchitecture and logic design of the CPU to ensure that it meets the

specified functional and performance requirements. Draft comprehensive test plans that

include assertions, irritators, and coverage points based on the CPU's microarchitecture

design. Develop functional testbenches in C, C++, and SystemVerilog to test the CPU's

functional units. Build testbench stimuli generators to exercise corner cases with unique

instruction sequences and data given the microarchitecture design. Use JasperGold

C2RTL and TCL to create formal testbenches for RISC-V standards. Debug RTL

assertions and mismatches to the golden model, and prepare detailed bug summaries for

the design team. Collaborate with the design and software teams to deliver and verify

any necessary fixes. Build the software toolchain to facilitate streamline the regression

testing process on simulation and emulation. Create custom software tools to collect

and summarize regression results for further analysis.

Master’s or foreign equivalent in Computer Engineering, Electrical Engineering, or related field

**Telecommuting allowed for this position**

Worksite:3315 Scott Blvd., Floor 4, Santa Clara, CA 90052

Applicant Instructions:Include job code 90052 in application. EOE.