Digital Design / DV Engineer

Role Overview:

The Platform IP Development group is seeking an experienced and highly technical engineer to develop key strategic IP for multiple business/product opportunities. The primary focus is on digital/mixed-signal design, including precision references, IOs, power, and mixed-signal/analog circuitry.

Key Responsibilities:

Design, simulate, and verify digital IP within mixed-signal IP environments.

Collaborate with analog engineers to create digital control, calibration, and interface circuits.

Develop RTL and analog models, digital macros, I/O interfaces, register and test maps, and verification collateral.

Work with digital back-end engineers on synthesis, scan test insertion, place-and-route, timing closure, verification, and timing model creation.

Document and present digital designs and results.

Define mixed-signal design best practices and optimize IP digital partitioning.

Support characterization/debugging in lab/ATE environments.

Collaborate with designers and teams across the company to support IP development and integration.

Qualifications:

MSEE or PhD in digital or mixed-signal IC design.

10+ years of relevant design experience in mixed-signal IC design.

Strong written and verbal communication skills.

Efficient and organized work methodology for optimal multi-tasking.

Understanding of mixed-signal design challenges and digital design requirements.

Proficiency with standard digital design/simulation tools and Cadence environment.

Problem-solving skills at all levels of design from gates to systems.

Ability to work independently and as part of a team.

Passion for learning different areas in design, applications, and products.

Familiarity with DV methodology and implementation.

Preferred Experience:

Analog-to-Digital (ADC, A/D), Digital-to-Analog (DAC, D/A), Phase-lock-loops (PLL), or similar mixed-signal blocks.

ADC/DAC calibration, FFT analysis, mixed-signal data, timing closure, clock-domain resynchronization, metastability analysis, PLL or clock-divider design.

Creating analog and/or mixed-signal models, AMS simulation, analog simulation, shared analog/digital testbench, sensor data, real or wreal models.