Sr. SOC Design Verification Engineer

Minimum Qualifications:

• Proven track record of first-pass silicon success in ASIC development cycles.

• Bachelor’s degree in computer science, Computer Engineering, or a related technical field (or equivalent experience).

• 8–10 years of hands-on experience with SystemVerilog and UVM methodology.

• Expertise in one or more verification areas such as SV Assertions, Formal Verification, or Emulation.

• Proficiency with EDA tools and scripting languages (Python, TCL, Perl, Shell) for building verification environments and flows.

Preferred Qualifications:

• Experience verifying CPU/GPU architectures.

• Background in developing UVM-based verification environments from scratch.

• Familiarity with data-center applications including Video, AI/ML, and Networking designs.

• Knowledge of revision control systems such as Git, Mercurial (Hg), or SVN.

• Experience verifying high-speed interfaces such as PCIe, DDR, and Ethernet.

• Strong collaboration skills with cross-functional teams (Design, Modeling, Emulation, and Validation).

Key Responsibilities:

• Define and implement SoC-level verification plans and build testbenches for subsystem/SoC verification.

• Develop and execute functional tests in alignment with test plans.

• Drive verification closure using defined metrics, including functional and code coverage.

• Debug and resolve design failures in close collaboration with design teams.

• Partner with cross-functional teams to ensure highest-quality designs.

• Continuously enhance verification processes by adopting latest industry tools, technologies, and methodologies.

Key Skills:
SystemVerilog, UVM, ASIC/SoC Verification, AI/ML, High-Speed Interfaces (PCIe, DDR, Ethernet), EDA Tools, Cad