Requirements

• Thorough knowledge of large scale on-chip fabric or on-chip interconnect architecture
• Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.
• Knowledge of cache coherent memory systems and interconnect.
• Familiarity with different on-chip network topologies (ring, mesh, xbar etc).
• Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as Python
• Experience with functional and performance simulators
• Knowledge of logic design principles along with timing and power implications
• Understanding of low power architecture techniques
• Understanding of high performance techniques and trade-offs in fabric architecture

Responsibilities

• Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specification
• Coherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth and latency targets
• Development, assessment, and refinement of Architecture to target power, performance, area, and timing goals
• Helping produce and review validation plans for functionality and performance

Education and experience

• PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
• This is an architecture lead position so a senior level of experience is expected.