RTL Design Engineer
Silicon Engineering
Posted on 3/15/2023

10,001+ employees

Designs, manufactures, & launches rockets and spacecrafts
Company Overview
SpaceX's mission is to make humanity multiplanetary. The company is working on a next generation of fully reusable launch vehicles that will be the most powerful ever built, capable of carrying humans to Mars and other destinations in the solar system.
Redmond, WA, USA
Experience Level
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 2+ years of experience working with ASICs and/or FPGAs
  • ASIC/FPGA system integration experience
  • Software design and development skills
  • Experience in designing DSP, digital communication system datapath blocks, and/or modem design
  • Excellent scripting skills (csh/bash, Perl, Python etc.)
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills
  • Ability to work long hours and weekends as necessary to support critical milestones
  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here
  • Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks
  • Implement or integrate design blocks using Verilog/SystemVerilog
  • Optimize designs for power, performance and area
  • Participate in the design process starting with high-level conceptual and architectural discussions and ending with micro architecture and design partition within the ASIC and/or FPGA
  • Participate in all phases of ASIC and/or FPGA design flow (e.g. synthesis, timing closure, verification)
  • Work with ASIC backend/implementation teams as needed
  • Bring-up and validate ASICs and FPGAs in the lab
  • Collaborate with software engineers in developing production software for your designs