Memory Characterization Engineer

• Generate timing collaterals for custom digital CMOS circuits utilizing industry-standard tools such as Liberate or Silicon-Spice. Analyze and validate characterized timing data.
• Perform statistical simulations to ensure the robustness of custom circuits.
• Participate in Silicon-Spice correlation activities to improve Performance, Power, Area (PPA) of custom digital circuits.
• Collaborate closely with the internal circuit design team and the System-on-a-Chip (SoC) team and understand customization requirements.
• Provide guidance and mentorship to junior and temporary engineers, as needed.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• 5 years of experience with Liberate MX or Nanotime timing tools and Spice or equivalent transistor level simulation tool.
• 3 years of experience in characterizing standard-cells or memory.
  
• Experience in writing spice decks and CMOS circuits.

Preferred qualifications:

• Master's degree in VLSI Integration, Computer Engineering, Electronics Engineering, or a related field.
  
• Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido.
  
• Experience with characterization tools (e.g., SiliconSmart, Liberate).
  
• Experience in PERL/Shell/TCL scripting or similar languages, with the ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages.
  
• Understanding of CMOS circuits and timing concepts (e.g., setup, hold).
  
• Understanding of Liberty Variation Format (LVF) and Composite Current Source (CCS) models.
  

In this role, you will develop custom silicon solutions that power the future of Google's direct-to consumer products. You'll contribute to the innovation behind products. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

You will be responsible for generating timing collaterals of custom SRAM/Register File Memory macros. You will collaborate with circuit designers to ensure the correctness of timing arcs. You will need to perform Spice simulations to validate the correctness of timing delays and power numbers. You will also be responsible for co-ordinating with the SOC team regarding the release of memory collaterals.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• 5 years of experience with Liberate MX or Nanotime timing tools and Spice or equivalent transistor level simulation tool.
• 3 years of experience in characterizing standard-cells or memory.
  
• Experience in writing spice decks and CMOS circuits.