Staff Engineer
RTL Design
Confirmed live in the last 24 hours
Austin, TX, USA
Experience Level
  • Demonstrated ability to develop and track realistic schedules, provide status reports, track and resolve issues is critical
  • Experience in all aspects of the RTL to silicon flow and have led teams in this area previously, specifically in the areas of RTL design, verification and implementation
  • Detailed knowledge of DFT design and deployment to production
  • Knowledge and experience developing verilog based RTL modules to be used within a larger SoC
  • Experience using advanced node rules, including power and testability support/optimization
  • Knowledge and experience with Synthesis tools/flows, including STA (static timing analysis), LEC, and CPF based designs
  • Knowledge and experience with C coding
  • Knowledge and experience with verification techniques and metrics, including coverage, assertions, RTL and gate level simulations, SDF annotations and general test plan generation and test case development using C, verilog, or UVM
  • Knowledge and experience with asynchronous, low power and multi-power domain techniques
  • Knowledge and experience with SDF based simulations and debug
  • Knowledge and experience using Linux based tools and scripting languages including git, perl, make, TCL and python
  • Experience with low power and analog design is preferred but not required
  • Design, verification and implementation of modules and/or subsystems used within the Ambiq SoC designs
  • Development will be done using verilog design language and will be implemented with the Cadence tool suite
  • Verification development will include creation, enhancement and maintenance of system verilog and UVM based test benches, supporting a wide variety of test stimulus and design abstraction levels (RTL/Gates/Models/FPGA)
  • Implementation of modules and design will include RTL synthesis and DFT insertion of digital designs at module, subsystem and system level, and timing analysis using STA tools in multiple modes of operation
  • Development, verification and support for DFT functions within the system. Will work with PE and TE engineers to develop and deploy cost effective production solutions for the Ambiq designs

201-500 employees