Staff Engineer

RTL Design

Confirmed live in the last 24 hours

Locations

Austin, TX, USA

Experience Level

Entry

Junior

Mid

Senior

Expert

Requirements

Demonstrated ability to develop and track realistic schedules, provide status reports, track and resolve issues is critical
Experience in all aspects of the RTL to silicon flow and have led teams in this area previously, specifically in the areas of RTL design, verification and implementation
Detailed knowledge of DFT design and deployment to production
Knowledge and experience developing verilog based RTL modules to be used within a larger SoC
Experience using advanced node rules, including power and testability support/optimization
Knowledge and experience with Synthesis tools/flows, including STA (static timing analysis), LEC, and CPF based designs
Knowledge and experience with C coding
Knowledge and experience with verification techniques and metrics, including coverage, assertions, RTL and gate level simulations, SDF annotations and general test plan generation and test case development using C, verilog, or UVM
Knowledge and experience with asynchronous, low power and multi-power domain techniques
Knowledge and experience with SDF based simulations and debug
Knowledge and experience using Linux based tools and scripting languages including git, perl, make, TCL and python
Experience with low power and analog design is preferred but not required

Responsibilities

Design, verification and implementation of modules and/or subsystems used within the Ambiq SoC designs
Development will be done using verilog design language and will be implemented with the Cadence tool suite
Verification development will include creation, enhancement and maintenance of system verilog and UVM based test benches, supporting a wide variety of test stimulus and design abstraction levels (RTL/Gates/Models/FPGA)
Implementation of modules and design will include RTL synthesis and DFT insertion of digital designs at module, subsystem and system level, and timing analysis using STA tools in multiple modes of operation
Development, verification and support for DFT functions within the system. Will work with PE and TE engineers to develop and deploy cost effective production solutions for the Ambiq designs

Company Overview:

Ambiq’s mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq’s goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq’s advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 200 million units as of March 2023. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, interesting, and challenging projects that will create a lasting impact. Come join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

Responsibilities:

Ambiq® is searching for an experienced Design Engineer to build and lead a small team of silicon design engineers developing products based on SPOT technology. The Design Engineer will report to the Director of Digital Engineering based in Austin, Texas and participate in the development of the products.

Specific Responsibilities:

Design, verification and implementation of modules and/or subsystems used within the Ambiq SoC designs.
Development will be done using verilog design language and will be implemented with the Cadence tool suite.
Verification development will include creation, enhancement and maintenance of system verilog and UVM based test benches, supporting a wide variety of test stimulus and design abstraction levels (RTL/Gates/Models/FPGA).
Implementation of modules and design will include RTL synthesis and DFT insertion of digital designs at module, subsystem and system level, and timing analysis using STA tools in multiple modes of operation.
Development, verification and support for DFT functions within the system. Will work with PE and TE engineers to develop and deploy cost effective production solutions for the Ambiq designs.

Qualifications:

Demonstrated ability to develop and track realistic schedules, provide status reports, track and resolve issues is critical.
Experience in all aspects of the RTL to silicon flow and have led teams in this area previously, specifically in the areas of RTL design, verification and implementation.
Detailed knowledge of DFT design and deployment to production.
Knowledge and experience developing verilog based RTL modules to be used within a larger SoC.
Experience using advanced node rules, including power and testability support/optimization.
Knowledge and experience with Synthesis tools/flows, including STA (static timing analysis), LEC, and CPF based designs.
Knowledge and experience with C coding.
Knowledge and experience with verification techniques and metrics, including coverage, assertions, RTL and gate level simulations, SDF annotations and general test plan generation and test case development using C, verilog, or UVM.
Knowledge and experience with asynchronous, low power and multi-power domain techniques.
Knowledge and experience with SDF based simulations and debug.
Knowledge and experience using Linux based tools and scripting languages including git, perl, make, TCL and python.
Experience with low power and analog design is preferred but not required.

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201-500 employees

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