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Full-Time

Senior Technologist RF IC Design Engineer

Posted on 6/27/2024

Western Digital

Western Digital

10,001+ employees

Provides high-performance data storage solutions

Data & Analytics
Hardware
Enterprise Software

Expert

Irvine, CA, USA

Category
Electronics Design Engineering
Electrical Engineering
Requirements
  • MSEE with 12+ years of experience in circuit design and development
  • Experience in full CMOS circuit design and development in various areas like baseband amplifiers, ADCs, high-speed drivers, power management, etc.
  • Experience in 40nm and below full CMOS technology
  • Track record of successful design releases and mass production
  • Thorough knowledge of industry standard EDA tools (Cadence, Mentor, etc.)
  • Experience with layout of high-performance analog blocks
  • Experience with floor planning, routing, and chip layout
  • Knowledge of high-performance analog layout techniques, EM-IR, and SOA considerations
  • Experience working with distributed design teams
  • Strong written and verbal communication skills
Responsibilities
  • Block level and transistor level circuit design and simulation
  • Layout supervision and verification
  • Preparation of test plan for the test group
  • Product characterization, reliability, and yield assessment
  • Simulation to bench and bench to test correlation
  • Bench evaluation at silicon and applications level
  • Documentation
  • Communicating with cross-functional groups

Western Digital specializes in high-performance data storage solutions, offering SSDs, HDDs, USB drives, and memory cards designed to power current technology and drive future innovations.

Company Stage

M&A

Total Funding

$927.9M

Headquarters

San Jose, California

Founded

2014

Benefits

Paid sick leave & vacation time

Medical/dental/vision insurance

Life, accident, & disability insurance

Tax-advantaged flexible spending and health savings accounts

Employee assistance program

Tuition reimbursement

Employee stock purchase plan

Western Digital Savings 401(k) Plan

INACTIVE