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Senior ASIC Design Engineer
Confirmed live in the last 24 hours
Locations
San Jose, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Computer Vision
Perl
Python
Verilog
FPGA
VHDL
Requirements
  • B.S. or M.S. in Electronic/Electrical Engineering with at least 5 years of working experience in ASIC design
  • Has deep knowledge of one or more of the following domains: Embedded CPU subsystem and architecture; High-speed digital signal processing, computer vision, or machine learning; High-performance serial interface protocols; Low power design methodology; Mixed-signal design; FPGA prototyping
  • Has strong RTL (Verilog/System Verilog/VHDL) coding skills, has hands-on experience in programming languages (Perl/Tcl/Python/C)
  • Has in-depth knowledge of high-speed digital design, multi-clock domain SOC and verification; Has a good understanding of ASIC design flow from RTL to silicon
  • Familiar with industry standard EDA tools; familiar with advanced silicon process & technology nodes for high speed and low power consumption
  • Has strong analytical skills and problem-solving ability, able to provide technical leadership as needed
  • A good and reliable team player with strong communication skills. Self-motivated, continually striving for excellence, and can thrive under pressure
Responsibilities
  • Partner closely with the functional R&D teams to develop design specification, documentation for individual function blocks, RTL implementation, system integration and set up and maintain verification environment
  • Be responsible fortasks including DFT, synthesis, static timing analysis, power estimation, hardware troubleshooting, silicon bring-up, and validation
  • Support new product introduction to the high-volume manufacturing process to enable automotive and non-automotive applications
Cepton Technologies

51-200 employees

ADAS LIDAR solutions company