Compensation Overview

Job Description:

As an RTL design engineer, you will collaborate with architects and implementation leads to define and implement RTL modules as required. Emphasis will be placed on minimizing power consumption while creating high quality, re-useable design.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Design and implement custom RTL modules for the Celestial SoC
• Author detailed design specification documents
• Collaborate with DV engineers on test requirements to ensure bug free designs
• Evaluate performance, area, and power tradeoffs
• Drive coverage closure for your designs

QUALIFICATIONS:

• 3 or more years logic design experience
• RTL design experience with SystemVerilog; familiarity with SVA
• Understanding of low power design techniques
• Knowledge of / Experience in Network Protocols
• Experience designing state machines, data paths, arbiters, and clock domain crossings
• Working knowledge of RTL quality assurance tools (Lint, CDC) and LEC preferred
• Proficient with scripting languages and task automation
• BS plus 3 years relevant experience. MS preferred

Location:  San Francisco Bay Area or Orange County, CA

For California location:

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity.  The target base salary for this role is approximately $135,000.00 - $155,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.