Job Description

In this position, the individual will contribute to pre-silicon verification related to next generation Storage Networking ASICs

• Verification Micro-architecture & Documentation for module level and system level test benches
• FW & HW co-simulations
• Test plan documentation
• Test bench coding and test writing
• Debugging module level and system level simulation failures
• RTL Code Coverage analysis and enhancements
• Scripting for automation and productivity improvements.
• Debug associated with FPGA and ASIC Validation (involves look at Ethernet and PCIe traces and detailed HW logging during system operation)

Qualifications

MUST HAVES

• 8-10 or more years’ experience in verification of storage and/or networking ASICs
• Strong communication skills, both verbal and written
• Proficiency with Verilog & System Verilog
• Proficiency with UVM is a must
• Experience in architecting test bench environments for unit and system level verification
• Strong protocol knowledge in one or more of the following areas: NVMe over fabrics, NVMe, TCP/IP, SCSI, Fibre Channel, Ethernet, SAS, SATA, RDMA, and PCIe protocols
• Knowledge of TLS, IP Security protocols and Root of Trust (RoT) is a plus.
• Proven track record with writing detailed test plans
• Problem solving skills and out-of-the-box thinking to test and validate RTL
• Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis