Summer Intern
ML
Confirmed live in the last 24 hours
Locations
San Jose, CA, USA
Experience Level
Intern
Requirements
- Well-rounded knowledge of ASIC design and EDA working flow
- Experience of physical design automation, Tcl or Perl scripting, MS Office
- VLSI design experience and RTL design using Verilog HDL preferred
- Excellent problem-solving skills with a proactive can-do attitude
- Currently pursuing MS in EE, CE, or equivalent
Responsibilities
- We offer amazing opportunities to grow, focusing on the three-dimensional integrated circuits (3DIC) development with Machine Learning application
- Detailed understanding of physical design automation flow and EDA tool functions
- Running and testing EDA tools in various technical areas to qualify the flow automation
- Generating feedback for bug fixes, enhancements, and improvement
- Developing documentation for knowledge sharing, training, and tool quality assurance
- Tracking project schedule and progress according to scope of work and phases