Staff Engineer
Design Verification
Confirmed live in the last 24 hours
Austin, TX, USA
Experience Level
  • BSEE/MSEE Degree 8-12 years of experience at block, sub-system and full-chip verification
  • Strong in understanding multiple architectures, integrate 3rd party IP's/VIP's, have worked with mixed-signal designs with low-power design and verification challenges
  • Strong understanding/exposure to Design Verification for low-power battery operated designs highly desired
  • C based verification in an SoC environment is required
  • Languages:SystemVerilog (UVM), Verilog, C/C++, , Perl, Python, Makefile
  • Technologies: ARM SoC (Preferred), AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, QoS
  • Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power
  • Ideal candidate should have demonstrated successful design verification tasks at block, sub-system, and full-chip level
  • Must have participated in all phases of chip development, from creating test plans, creating test bench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding
  • Utilize UVM to create drivers, monitors, predictors, and scoreboards
  • In-Depth knowledge of SoC architecture with AMBA AXI/AHB/APB, DMA's, Security, clock, and power-gating techniques is required
  • Responsible for verification of block(s) that includes writing tests, assertion and coverage for a block
  • Create tests to achieve coverage goals while verifying functionality
  • Develop support utilities for verification automation, test bench automation, regression, to improve productivity
  • Develop tests to evaluate power and performance aspects of the design
  • Perform gate-level-simulations and participate in supporting FPGA and Post-silicon bring-up
Desired Qualifications
  • Experience with ARM processor-based designs and low-power design techniques is a plus

201-500 employees